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Proceedings Papers

Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging

Yu Hung Huang, Huei-Huang Lee, Sheng-Jye Hwang, Durn-Yuan Huang

Proc. ASME. InterPACK2009, ASME 2009 InterPACK Conference, Volume 1, 9-14, July 19–23, 2009

Publisher: American Society of Mechanical Engineers

Paper No: InterPACK2009-89163

https://doi.org/10.1115/InterPACK2009-89163

View Paper titled, Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging

Topics: Copper, Packaging, Plating, Silicon

Proceedings Papers

Mold Adhesion Force Measurement

Huei-Huang Lee, Sheng-Jye Hwang, Durn-Yuan Huang, Yeong-Jyh Lin

Proc. ASME. InterPACK2007, ASME 2007 InterPACK Conference, Volume 1, 51-58, July 8–12, 2007

Publisher: American Society of Mechanical Engineers

Paper No: IPACK2007-33826

https://doi.org/10.1115/IPACK2007-33826

View Paper titled, Mold Adhesion Force Measurement

Topics: Adhesion, Force measurement, Coatings, Molding, Engineers, Instrumentation, Temperature, Foundry coatings, Surface finishing, Cavities

Proceedings Papers

Simulation of Warpage Considering Both Thermal and Cure Induced Shrinkage During Molding in IC Packaging

Shiang-Yu Teng, Sheng-Jye Hwang

Proc. ASME. InterPACK2005, Advances in Electronic Packaging, Parts A, B, and C, 867-872, July 17–22, 2005

Publisher: American Society of Mechanical Engineers

Paper No: IPACK2005-73062

https://doi.org/10.1115/IPACK2005-73062

View Paper titled, Simulation of Warpage Considering Both Thermal and Cure Induced Shrinkage During Molding in IC Packaging

Topics: Integrated circuit packaging, Molding, Shrinkage (Materials), Simulation, Warping, Pressure, Simulation models, Temperature, Thermal expansion

Journal Articles

Simulations of Process-Induced Warpage During IC Encapsulation Process

Shiang-Yu Teng, Sheng-Jye Hwang

Publisher: ASME

J. Electron. Packag. September 2007, 129(3): 307–315.

https://doi.org/10.1115/1.2753936

Published Online: December 11, 2006

View Article titled, Simulations of Process-Induced Warpage During IC Encapsulation Process

Topics: Shrinkage (Materials), Simulation, Warping, Temperature

Journal Articles

Three-Dimensional Paddle Shift Modeling for IC Packaging

Chien-Chang Pei, Sheng-Jye Hwang

Publisher: ASME

J. Electron. Packag. September 2005, 127(3): 324–334.

https://doi.org/10.1115/1.1938986

Published Online: December 2, 2004

View Article titled, Three-Dimensional Paddle Shift Modeling for IC Packaging

Topics: Computation, Deflection, Flow (Dynamics), Fluid dynamics, Geometry, Integrated circuit packaging, Integrated circuits, Mesh generation, Modeling, Molding

Journal Articles

Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect

Chien-Chang Pei, Sheng-Jye Hwang

Publisher: ASME

J. Electron. Packag. September 2005, 127(3): 335–339.

https://doi.org/10.1115/1.1939028

Published Online: November 3, 2004

View Article titled, Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect

Topics: Density, Wire, Flow (Dynamics)

Journal Articles

Computer-Aided Design of a TSOP II LOC Package Using Taguchi’s Parameter Design Method to Optimize Mold-Flow Balance

Hung-Lung Lee, Shyang-Jye Chang, Sheng-Jye Hwang, Associate Professor,, Francis Su, S. K. Chen

Publisher: ASME

J. Electron. Packag. June 2003, 125(2): 268–275.

https://doi.org/10.1115/1.1569957

Published Online: June 10, 2003

View Article titled, Computer-Aided Design of a TSOP II LOC Package Using Taguchi’s Parameter Design Method to Optimize Mold-Flow Balance

Topics: Computer-aided design, Design, Design methodology, Flow (Dynamics), Taguchi methods, Noise factors, Molding, Packaging, Simulation, Manufacturing

Journal Articles

An Efficient Solution for Wire Sweep Analysis in IC Packaging

Jerry Su, Sheng-Jye Hwang, Associate Professor, Francis Su, Shou-Kang Chen

Publisher: ASME

J. Electron. Packag. March 2003, 125(1): 139–143.

https://doi.org/10.1115/1.1535447

Published Online: March 14, 2003

View Article titled, An Efficient Solution for Wire Sweep Analysis in IC Packaging

Topics: Wire, Flow (Dynamics), Integrated circuits, Integrated circuit packaging

Journal Articles

Study of P-V-T-C Relation of EMC

Yi-San Chang, Sheng-Jye Hwang, Huei-Huang Lee, Durn-Yuan Huang

Publisher: ASME

J. Electron. Packag. December 2002, 124(4): 371–373.

https://doi.org/10.1115/1.1498266

Published Online: December 12, 2002

View Article titled, Study of P-V-T-C Relation of EMC

Topics: Differential scanning calorimetry, Molding, Pressure, Shrinkage (Materials), Temperature, Thermal expansion, Epoxy resins, Chemical kinetics, Viscosity

Journal citation

NARROW

Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging

Mold Adhesion Force Measurement

Simulation of Warpage Considering Both Thermal and Cure Induced Shrinkage During Molding in IC Packaging

Simulations of Process-Induced Warpage During IC Encapsulation Process

Three-Dimensional Paddle Shift Modeling for IC Packaging

Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect

Computer-Aided Design of a TSOP II LOC Package Using Taguchi’s Parameter Design Method to Optimize Mold-Flow Balance

An Efficient Solution for Wire Sweep Analysis in IC Packaging

Study of P-V-T-C Relation of EMC

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