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TECHNICAL PAPERS

J. Electron. Packag. 2000;123(3):165-172. doi:10.1115/1.1371923.

Heat transfer from a discrete heat source to multiple, normally impinging, confined air jets was experimentally investigated. The jets issued from short, square-edged orifices with still-developing velocity profiles on to a foil heat source which produced a constant heat flux. The orifice plate and the surface containing the heat source were mounted opposite each other in a parallel-plates arrangement to effect radial outflow of the spent fluid. The local surface temperature was measured in fine increments over the entire heat source. Experiments were conducted for different jet Reynolds numbers (5000<Re<20,000), orifice-to-target spacing (0.5<H/d<4), and multiple-orifice arrangements. The results are compared to those previously obtained for single air jets. A reduction in orifice-to-target spacing was found to increase the heat transfer coefficient in multiple jets, with this effect being stronger at the higher Reynolds numbers. With a nine-jet arrangement, the heat transfer to the central jet was higher than for a corresponding single jet. For a four-jet arrangement, however, each jet was found to have stagnation-region heat transfer coefficients that were comparable to the single-jet values. The effectiveness of single and multiple jets in removing heat from a given heat source is compared at a fixed total flow rate. Predictive correlations are proposed for single and multiple jet impingement heat transfer.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2001;123(3):173-181. doi:10.1115/1.1377271.

A means to properly size rectangular heat spreaders between a dielectric layer connected to thermal ground and a power device is developed by modeling the problem as a thermal resistance network. Generalized formulas and nondimensional charts to optimize heat spreader thickness and footprint are presented. The power device and heat spreader are assumed to be (concentric) rectangular solids of arbitrary length, width and thickness. The nondimensional results are validated by finite element analysis (FEA) and examples demonstrate the utility of the methodology to thermal design engineers.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):182-188. doi:10.1115/1.1347993.

Three analytical models are presented for determining laminar, forced convection heat transfer from isothermal cuboids. The models can be used over a range of Reynolds number, including at the diffusive limit where the Reynolds number goes to zero, and for a range of cuboid aspect ratios from a cube to a flat plate. The models provide a simple, convenient method for calculating an average Nusselt number based on cuboid dimensions, thermophysical properties and the approach velocity. Both the cuboid and the equivalent flat plate models are strongly dependent upon the flow path length which is bounded between two easily calculated limits. In comparisons with numerical simulations, the models are shown to be within ±6 percent over the range of 0≤ReA≤5000 and aspect ratios between 0 and 1.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):189-195. doi:10.1115/1.1348010.

The air flow rate available for cooling of notebook computers is very limited. Thus, notebook computer manufacturers desire a “passive” cooling method. Heat pipes are typically used to transport the heat from the CPU to a forced convection, air-cooled condenser. This paper describes a passive, keyboard sized aluminum Integrated Plate Heat Pipe (IP-HP) that has been developed for notebook computers. Analysis was performed to estimate the several thermal resistances in the heat pipe, including the effect of the vapor pressure drop. The modified design using a heat spreader at the evaporator significantly reduces the heat pipe resistance. Further work was done to evaluate the thermal contact resistance at the IP-HP/CPU interface. Test results show that the IP-HP can reject 18 W while maintaining the CPU 65°C above ambient temperature.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):196-199. doi:10.1115/1.1347987.

An optical method was developed to measure the two-dimensional (2D) surface curvatures of electronic packages by employing four laser beams. Each laser beam measures the slopes of the surface at the incident point along two perpendicular directions. By combining four pairs of slopes, the 2D surface curvatures of the package can be calculated. The surface warpage of an underfilled flip-chip package during thermal cycling was measured by this method and the result was verified by finite element analysis (FEA). Both experimental and FEA results show that the surface warpage is almost a linear function of temperature between 25°C and 150°C for the measured package.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(3):200-210. doi:10.1115/1.1348337.

This paper introduces a general computational model for electronic packages, e.g., cabinets that contain electronic equipment. A simplified physical model, which combines principles of classical thermodynamics and heat transfer, is developed and the resulting three-dimensional differential equations are discretized in space using a three-dimensional cell centered finite volume scheme. Therefore, the combination of the proposed simplified physical model with the adopted finite volume scheme for the numerical discretization of the differential equations is called a volume element model (VEM). A typical cabinet was built in the laboratory, and two different experimental conditions were tested, measuring the temperatures at forty-six internal points. The proposed model was utilized to simulate numerically the behavior of the cabinet operating under the same experimental conditions. Mesh refinements were conducted to ensure the convergence of the numerical results. The converged mesh was relatively coarse (504 cells), therefore the solutions were obtained with low computational time. The model temperature results were directly compared to the steady-state experimental measurements of the forty-six internal points, with good quantitative and qualitative agreement. Since accuracy and low computational time are combined, the model is shown to be efficient and could be used as a tool for simulation, design, and optimization of electronic packages.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):211-217. doi:10.1115/1.1370376.

A thermal analysis has been performed for a package design pertinent to power electronics. The objective has been the derivation of straightforward expressions that relate the materials used and their physical dimensions to the power input and the junction temperature. This has been done for both steady-state operating conditions and for pulses. The role of phase change materials (PCMs) in suppressing temperature elevations during pulses is also addressed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(3):218-224. doi:10.1115/1.1362674.

Multi-layered stacks are commonly used in microelectronic packaging. Traditionally, these systems are designed using linear-elastic analysis either with analytical solutions or finite element method. Linear-elastic analysis for layered structures yields very conservative results due to stress singularity at the free edge. In this paper, it is shown that a damage mechanics based nonlinear analysis not just leads to a more realistic analysis but also provides more accurate stress distribution. In this paper these two approaches are compared. Moreover, mesh sensitivity of the finite element analysis in stack problems is studied. It is shown that the closed form and elastic finite element analyses can only be used for preliminary studies and elastic finite element method is highly mesh sensitive for this problem. In elastic analysis the stress singularity at the free edge makes mesh selection very difficult. Even when asymptotic analysis is used at the free edge, the results are very conservative compared to an inelastic analysis. Rate sensitive inelastic analysis does not suffer from the stress singularity and mesh sensitivity problems encountered in elastic analysis.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):225-231. doi:10.1115/1.1348012.

This paper reports the results of CFD analysis to cool the 30-W socketed CPU of a desktop computer with minimum air flow rate and minimum heat sink size. This was achieved using only the fan in the power supply for all air movement in the chassis. A duct was employed to direct the air flow over the CPU and then to the inlet air vents of the power supply. Use of this duct allowed more than 10°C reduction of the CPU case temperature, relative to an unducted design. The CFD analysis results were confirmed by experiment, and the predicted CPU case temperatures agreed within ±2.9°C of the experimental values for the ducted cases. This paper describes the methodology of CFD analysis for the heat sink/duct design, and describes experimental procedures to validate the predictions.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):232-237. doi:10.1115/1.1349423.

A detailed model of a die-up 256-pin Plastic Ball Grid Array (PBGA) package was created and validated against experimental data for natural convection and forced convection environments. Next, four compact models were derived; two two-resistor models (one created through a two-point computational cold plate test; the other using the DELPHI optimization approach), a multi-resistor Star network model and a shunt network model. The latter three models were derived using the methodology established by the DELPHI (Development of Libraries of Physical models for an Integrated design environment) project. The four compact models and the detailed model were each placed in natural convection and forced convection (velocities of 1,2, and 4 m/s) environments. Good agreement was obtained for the die-junction temperature rise for both the detailed and the shunt compact models. The star and two-resistor models were seen to be inferior in terms of accuracy. The two-resistor model created using the DELPHI methodology was found to be superior compared to the one created with the computational cold-plate test. The star model showed little gain in performance as compared to the DELPHI two-resistor model.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):238-246. doi:10.1115/1.1371232.

The time- and temperature-dependent deformation behavior of two Sn-Ag base alloys, 96Sn-4Ag and Castin (96.2Sn-2.5Ag-0.8Cu-0.5Sb), used as solder interconnect materials was determined over strain rates ranging from 10−6 s−1 to 10−2 s−1 and temperatures ranging from −55°C–125°C. Uniaxial strain rate jump tests along with isothermal and thermomechanical cyclic tests were conducted. The constitutive behavior of each alloy was modeled with both a simple power law creep equation and the McDowell unified creep-plasticity model. Accumulated deformation under unconstrained thermal cycling was also measured to determine the relative dimensional stability due to internal constraints in the alloy itself. Overall, the Castin alloy appeared to be more stable and was more resistant to inelastic deformation.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1998;123(3):247-253. doi:10.1115/1.1371781.

A unified viscoplastic constitutive law, the Anand model, was applied to represent the inelastic deformation behavior for solders used in electronic packaging. The material parameters of the constitutive relations for 62Sn36Pb2Ag, 60Sn40Pb, 96.5Sn3.5Ag, and 97.5Pb2.5Sn solders were determined from separated constitutive relations and experimental results. The achieved unified Anand model for solders were tested for constant strain rate testing, steady-state plastic flow and stress/strain responses under cyclic loading. It is concluded that the Anand model can be applied for representing the inelastic deformation behavior of solders at high homologous temperature and can be recommended for finite element simulation of the stress/strain responses of solder joints in service.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):254-259. doi:10.1115/1.1348019.

Wiresaw has emerged as a leading technology in wafer preparation for microelectronics fabrication, especially in slicing large silicon wafers (diameter≥300 mm) for both microelectronic and photovoltaic applications. Wiresaw has also been employed to slice other brittle materials such as alumina, quartz, glass, and ceramics. The manufacturing process of wiresaw is a free abrasive machining (FAM) process. Specifically, the wiresaw cuts brittle materials through the “rolling-indenting” and “scratch-indenting” processes where the materials removal is resulting from mechanical interactions between the substrate of the workpiece and loss abrasives, which are trapped between workpiece and wire. Built upon results of previous investigation in modeling of wiresaw, a model of wiresaw slicing is developed based on indentation crack as well as the influence of wire carrying the abrasives. This model is used to predict the relationship between the rate of material removal and the mechanical properties of the workpiece together with the process parameters. The rolling, indenting, and scratching modes of materials removal are considered with a simple stochastic approach. The model provides us with the basis for improving the efficiency of the wiresaw manufacturing process based on the process parameters.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):260-267. doi:10.1115/1.1349422.

Reliability of epoxy molding compounds used in plastic packages of integrated circuit (IC) devices depends to a great extent on the level of thermal stresses. These are due primarily to the thermal expansion (contraction) mismatch of the epoxy and the silicon materials. In this analysis we assess the effect of silica fillers on the level of thermal stresses. We conclude that thermal stresses in the compound can indeed be reduced by the application of appropriate fillers. We found that the filler volume concentration does not have to be larger than 30 percent to keep the thermal stresses at a sufficiently low level. This number is close to the filler volume concentration of 30–40 percent in commercially available molding compounds. The obtained results and recommendations can be helpful in the analysis of stresses in, and physical design of, plastic packages.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(3):268-272. doi:10.1115/1.1349421.

Variation of processing conditions on warpage prediction of a plastic quad flat package (PQFP) is examined. Thermal mismatch between package constituent materials is the major cause of IC package warpage. To minimize the warpage problem, a thorough understanding of epoxy molding compound (EMC) properties with molding parameters is necessary as EMC is epoxy-based with time and temperature dependent viscoelastic properties. This paper first addressed the thermal characterization of encapsulating material. Degree-of-cure (DOC or β), coefficient of thermal expansion (CTE or α), glass transition temperature Tg, and shear modulus G and G of the molded specimens were measured by various thermal analysis techniques. The glass transition temperature was shown to be a good and direct measure of the degree-of-cure. The CTEs 1 and α2),G and G were found to be decreasing functions of degree-of-cure. Viscoelastic EMC material models with DOC (i.e., Tg) dependent were formulated. Package warpage predictions against different processing conditions were performed via finite element analyses. Out-of-plane displacement measurements were performed on plastic quad flat package (PQFP) to validate the numerical results. Warpage prediction by the viscoelastic material model was found to agree with the measured data better than the thermoelastic one. For a given cured content, less warpage was found in packages molded at low temperature and longer molding time OR high temperature and shorter molding time.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):273-277. doi:10.1115/1.1347986.

The present study examines the relationship between thermal conductivity and planarity in polyimide films. The samples tested were specially prepared to range in orientation from three dimensionally random to highly planar. The molecular structure and orientation of the polyimide film have been characterized by polarizing microscope techniques, while the thermal conductivity measurements were done using a new rapid nondestructive technique. This correlation represents the first time thermal conductivity has been measured by modified hot wire techniques and related to the internal structure of polyimide. This work contributes to a deeper theoretical understanding of thermal conductivity and heat transfer mechanisms as they relate to orientation. Thermal conductivity evaluation could provide a new tool in the arsenal of structural characterization techniques. This relationship between thermal conductivity and orientation is key for applications of directional heat dissipation in the passive layers of chip assemblies. Such a correlation has potential to speed the development cycles of new materials during formulation as well as assure properties during production.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(3):278-283. doi:10.1115/1.1372319.

This paper presents a viscoplasticity model taking into account the effects of change in grain or phase size and damage on the characterization of creep damage in 60 Sn-40 Pb solder. Based on the theory of damage mechanics, a two-scalar damage model is developed for isotropic materials by introducing the free energy equivalence principle. The damage evolution equations are derived in terms of the damage energy release rates. In addition, a failure criterion is developed based on the postulation that a material element is said to have ruptured when the equivalent damage accumulated in the element reaches a critical value. The damage coupled viscoplasticity model is discretized and coded in a general-purpose finite element program known as ABAQUS through its user-defined material subroutine UMAT. To illustrate the application of the model, several example cases are introduced to analyze, both numerically and experimentally, the tensile creep behaviors of the material at three stress levels. The model is then applied to predict the deformation of a notched specimen under monotonic tension at room temperature (22°C). The results demonstrate that the proposed model can successfully predict the viscoplastic behavior of the solder material.

Commentary by Dr. Valentin Fuster

PAPERS ON RELIABILITY

J. Electron. Packag. 1999;123(3):284-289. doi:10.1115/1.1371782.

To investigate the effect of stencil thickness and reflow ambient atmosphere on the reliability of ceramic ball grid array (CBGA) assemblies, three levels of stencil thickness, 0.10, 0.15, and 0.20 mm, were used to print solder paste on printed circuit board (PCB). After the CBGA modules were placed on PCBs, the specimens were divided into two groups, and reflowed in nitrogen and compressed air separately. Properties of the six groups of assemblies, such as shear strength, bending fatigue life, thermal shock cycles, and vibration fatigue life, were tested to find out the optimum assembling process. The results show that assemblies prepared with a stencil 0.15 mm thick yield maximized performance. And the nitrogen ambient atmosphere demonstrates a remarkable effect on improving the fatigue life. Theoretical models are given to qualitatively explain the relationship between the solder joint volume and performance. This work provides a guideline on how to determine the soldering process parameters of CBGA assemblies.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(3):290-294. doi:10.1115/1.1347997.

The shear cycle fatigue lifetimes of plastic ball grid array (PBGA) solder joints formed using different reflow profiles are studied in this paper. The profiles were devised to have the same “heating factor” but to have different conveyor speeds. The test results show that, by increasing the conveyor speed during reflow, the shear fatigue lifetime of solder joints can be improved substantially. On the other hand, the fatigue lifetime of the test specimens decreased with increasing the cycle displacement amplitude. Heat transmission analysis shows that increasing conveyor speed increases the cooling rate during solder solidification. SEM micrographs reveal that cracks initiated at the acute point near the PCB solder pad, then propagate along the interface of the bulk solder/IMC layer. The test results are ascribed to roughing interface of the bulk solder/IMC of the solder joints that results on increasing the cooling rate. The frictional sliding mechanism is used to explain the test results.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):295-301. doi:10.1115/1.1348338.

Using detailed finite element models, a fracture analysis of solder bumps and under bump metallurgy (UBM) in flip-chip packages is carried out. Our objective is to identify likely fracture modes and potential delamination sites at or near these microstructural components. In order to study flip-chips, whose dimension spans from sub-micron thickness UBM layers to several millimeters wide package, we have applied a multi-scale finite element analysis (MS-FEA) procedure. In this procedure, initially, deformation of whole thermally loaded package is analyzed. Then, the results are prescribed as the boundary conditions in a very detailed cell model, containing a single solder bump, to investigate micro-deformation surrounding UBM. Using the models with two different scales, accurate stress fields as well as fracture parameters of various interface cracks can be determined. The MS-FEA is ideally suited for the flip-chip packages since they contain many identical solder bumps. A cell model can be repeatedly used to probe stress and fracture behaviors at different locations. The computed results show high stress concentrations near the corners of solder bumps and UBM layers. Based on the energy release rate calculations, solder bumps located near the edge of chip are more likely to fail. However, our results also suggest possible delamination growth at solder bumps near the center of chip. In addition, we have observed increasing energy release rates for longer cracks, which implies a possibility of unstable crack growth.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(3):302-308. doi:10.1115/1.1362673.

This study investigates the effect of quasi-static bending loads (strain rate=0.05/s) on the durability of 0.5 mm pitch Chip Scale Package (CSP) interconnects when assembled on FR4 substrates. The substrates have rows of CSPs and are subjected to three-point bending loads. Overstress curvature limits are experimentally determined and used to identify limits for zero-to-max cyclic bending loads. The test configuration is simulated using finite element modeling (FEM) and the total strain accumulated in the solder joints is estimated. Using the FEM model, a calibration curve is constructed to relate the cyclic curvature range in the substrate to the cyclic strain range in the critical solder joint. Bending moments along the substrate are estimated from the forces applied at the center of the board during the fatigue test. Strains measured on the substrate surface and the bending displacements measured at the center are used to estimate curvatures at different locations along the substrate. Using the calibration curve, the total strains in the solder joint are obtained for the applied loading. A strain-range fatigue damage model proposed by Coffin and Manson, is used to predict the cycles to failure for the applied loading. Predicted durability is compared to experimental measurements. Concave substrate curvature is found to be more damaging than convex curvature, for interconnect fatigue. Finite element simulations are repeated for life-cycle loading to predict acceleration factors. Using the acceleration factors, the product durability is estimated for life-cycle environments.

Commentary by Dr. Valentin Fuster

TECHNICAL BRIEFS

J. Electron. Packag. 2000;123(3):309-311. doi:10.1115/1.1371925.

Thermal interface pastes based on silicone, lithium doped polyethylene glycol (PEG), and sodium silicate were evaluated in their performance before and after heating up to 120°C. The thermal contact conductance of any of the pastes between copper disks decreased after heating, such that the fractional decrease was less for the silicone-based paste than the PEG-based and sodium-silicate-based pastes. Nevertheless, the conductance was lower for the silicone-based paste than the other pastes both before and after heating up to 100 cycles.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(3):311-315. doi:10.1115/1.1371780.

The stress ratio effect on the fatigue crack growth behavior of 95Pb-5Sn solder has been investigated. It is found that both ΔJ and ΔK can correlate fatigue crack growth data well, which means that the crack growth behavior of the 95Pb-5Sn solder under the frequency of 10 Hz was dominantly cyclic dependent. The da/dN-ΔJ relationship can be expressed as: da/dN=1.1×10−11⋅ΔJ1.45. Low level of crack closure was found only in the near-threshold region. Except in this region, no crack closure was observed in the present test conditions. Both transgranular and intergranular fractures were observed on fracture surfaces: the former was dominant in most test conditions and the latter was dominant at the high stress ratio of 0.7. Striations and striation-like features were also found. Many slip bands and cavities along the grain boundary were observed on the crack wake and ahead of the crack tip in the high crack growth rate region.

J. Electron. Packag. 1999;123(3):315-318. doi:10.1115/1.1371924.

A numerical method for simulating impinging air flow and heat transfer in plate-fin type heat sinks has been developed. In this method, all the fins of an individual heat sink and the air between them are replaced with a single, uniform element having an appropriate flow resistance and thermal conductivity. With this element, fine calculation meshes adapted to the shape of the actual heat sink are not needed, so the size of the calculation mesh is much smaller than that of conventional methods.

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