Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Metamaterials are structures that are artificially engineered to obtain properties that are not available in nature. For instance, advances in optical metamaterials have allowed sophisticated control over light or electromagnetic waves. As one of the most influential and popular benchmarks, an invisibility cloak, has been achieved at both microwave regimes [1,2] and optical frequencies [3–8] based on the theory of transformation optics. Coordinate transformation-based methodologies connect metamaterial properties with thermal dissipation in devices, which further inspires the study of thermal metamaterials for heat control. Various thermal metamaterials that are conduction-based have been demonstrated through numerical [9–11] or experimental [12–15] studies under steady-state or transient conditions. Additionally, scattering cancelation-based bilayer thermal cloaks have been experimentally demonstrated in 2D [16,17] or 3D [17,18]. Topology optimization-based finite element methods have also been explored to enable heat flow control in arbitrary (e.g., noncircular or nonspherical) geometries [19,20] and bifunctional cloaking [21]. The combined manipulating of thermal and dc fields [22], as well as, thermal-composite design optimization methods for thermal management of printed circuit board (PCB)-based electronics [23] have been considered. Thermal radiation-based metamaterials have been actively studied [24] but not been reviewed in this paper due to their limited relevance to electronic packaging at the present.

Indeed, thermal metamaterials can make an impact on electronic packaging [25]. With rapid development of nanoelectronics, 3D-integrated circuits (ICs), and flexible electronics, thermal management is becoming more challenging [26]. For example, in 2.5D packages, the logic power as well as the number of high band width memory (HBM) layers continue to increase [27,28]. One critical challenge in 2.5D packages is thermal crosstalk as the logic chip and HBM are placed close to each other while they require different operating temperatures [29,30]. Thus, thermal metamaterials are needed to facilitate heat dissipation and protect temperature-sensitive components [31–33]. In 3D packages, thermal resistances and operating temperatures continue to increase. Conventional thermal management approaches include through-silicon-via optimization [34–40] and single- or two-phase cooling with microchannels [41–46].

In this paper, we review and summarize the recent progress, and outlook, of thermal metamaterials as related to challenges in thermal management of electronic packaging. In Sec. 2, we review thermal metamaterials with a focus on anisotropic heat spreaders and diffusers, thermal cloaking and isolating, and heat guiding and bending devices. This section discusses theoretical and experimental advancements and thermal metamaterials that are related to packaging applications. In Sec. 3, we review the thermal management challenges in heterogeneous integration with a focus on multichip implementations and multilayer stacking. In Sec. 4, we discuss package-level cooling capacities and implications of thermal metamaterials for packaging applications and potential research directions in the future.

In the last decade, there have been significant advances in the field of thermal metamaterials. The trend in thermal metamaterials has been toward practical demonstrations such as thermostats [47], thermal camouflage [48], dual-function thermal metamaterials [49], and active heat flow control [50,51]. In this section, we review the recent progress in conduction-based thermal metamaterials that are relevant to potential applications in electronic packaging.

The ability to control thermal energy through mediums has significant implications beyond fundamental study. The controlled transmission of heat is hard to achieve in one material or device because heat is carried by a broad spectrum of high-frequency (terahertz) phonons that are hard to control [52]. Moreover, microscale heat transport in solids is diffusive based on the Fourier's law of heat conduction: $qi=−kij∇Tj$⁠, where $kij$ represents the second-order thermal-conductivity tensor. Here, $qi$ and $∇Tj$ are the heat flux and temperature gradient in the ith and jth directions, respectively. The path of heat conduction can be controlled by engineering an artificial material with prescribed anisotropy in its thermal-conductivity tensor.

With respect to functional devices based on thermal passage, Chang et al. first fabricated thermal diodes using carbon nanotubes and boron nitride nanotubes [53]. The nonuniform mass deposited along the tube yielded a higher conductance when heat flows from the high-mass region to the low-mass region. Some 2D materials like black phosphorous had also shown thermal-conductivity anisotropy arising from the anisotropic phonon dispersion relation [54,55].

In recent studies, silicon nanostructures with vertically etched holes, or holey silicon, had demonstrated significant thermal-conductivity reductions and anisotropic thermal conductivity in the in-plane and cross-plane directions [56–58]. Ren and Lee had shown that the unique thermal-conductivity anisotropy in holey silicon is ideal for thermoelectric cooling (TEC) to address on-chip hot spots [59,60]. In the in-plane direction, the neck size dominated phonon boundary scattering reduces the thermal conductivity (k_x and k_y), which sustains a large temperature gradient for enhanced thermoelectric effects. In the cross-plane direction, the low frequency (long wavelength) phonons are less susceptible to surface disorder. The persistent long wavelength phonons lead to a high cross-plane thermal conductivity (k_z), which facilitates heat dissipation. To address such increasingly severe hot spot issues in nanoscale and high-power electronics, a lateral TEC design based on holey silicon is shown in Fig. 1(a). The heat generation by electronics was modeled by a combination of a 70 W · cm⁻² background heat flux and a 700 W · cm⁻² hot spot heat flux as representative values for future electronics. The top of holey silicon undergoes convective heat transfer to 25 °C ambient air with a constant/equivalent convection coefficient value of 8700 W · m⁻²K⁻¹, which represents the use of an advanced heat exchanger [61]. With an optimal applied current, the hot spot temperature of the holey silicon-based TEC was 15 °C lower compared to that of the bulk silicon-based TEC; see Fig. 1(d). Holey silicon-based TEC can be potentially used to provide localized cooling to power electronics and optoelectronic devices [16,61].

Anisotropic heat spreaders/diffusers can also be designed through the metamaterial approach for passive cooling applications. Vemuri and Bandaru reported a perfect thermal diffuser by rationally placing constituent materials in the radial and the azimuthal directions [62]. Figure 1(b) shows the design of thermal diffuser. When a hot spot heat flux is applied at the center, the isotherm lines are equally spaced through the spreader; see Fig. 1(e). The source temperature of the anisotropic heat spreader is significantly lower compared to that obtained using a single material with isotropic thermal conductivity. The advantage of such designs includes the regularization of heat transport, so as to control the path of heat transfer, e.g., to obtain a uniform temperature distribution avoiding hot spots. The facilitating methodology involves a metamaterial architecture, constituted from individual thermal meta-atoms at any given point in the diffuser and with spatially varying values for the thermal conductivity. Hamed and Ndao designed a bilayer thermal diffuser based on coordinate transformation to increase the thermal spreading efficiency [63]. Figure 1(c) shows the cross-sectional view of the heat spreader design with alternating layers of copper (k_Cu = 400 W · m⁻¹K⁻¹) and polydimethylsiloxane (PDMS, k_PDMS = 0.15 W · m⁻¹K⁻¹). With constant temperatures applied to the chip (T₁ = 80 °C) and spreader (T₂ = 27 °C) surfaces, the metamaterial heat spreader allows for much higher heat spreading to guide heat in the lateral direction compared to a pure Cu spreader reference, see Fig. 1(f).

In additional to cooling, efficient heat expanders are designed through coordinate transformation to provide a large surface of uniform temperature when there is a small hot spot. Liu et al. developed a plate heater based on transformation thermodynamics that can transiently provide a large and homogeneous-temperature surface powered by a thermal source whose area is 100 times smaller compared to that of the surface [64]. Han et al. constructed a thermal expander based on an elliptical thermal cloak that works as a high-efficiency point-to-plane heat source convertor with excellent transient performance [65].

Thermally sensitive elements, electronic circuits, components, or systems may be arranged to be in a region with minimum thermal disturbances, i.e., where the thermal gradient across the elements may be as close to zero as possible, irrespective of the temperature variations in the surroundings. A region where such a gradient may be established may be defined as a thermal cloak. The bending of the heat flux, through individual materials arrangement in a metamaterial immediately suggests applications [12] to thermal concentrators or thermal cloaks [11], where the temperature gradient could be engineered to be equal to zero in the cloaked region. Experimentally, a temperature gradient less than 0.004 K/cm was measured over the cloaked region [66]. Thermal invisibility cloak reduces temperature disturbance in the cloaked region and has the potential for many thermal management functions [22,67]. A majority of thermal cloaking research focuses on hiding the object from external heat flow. Fan et al. [68] and Chen et al. [69] first investigated thermal cloaking based on coordinate transformation methodologies, which indicates the required transformed properties in the physical space to realize invisibility [67]. Li et al. developed a bifunctional cloak possessing both electrical and thermal cloaking functionalities. The desired anisotropic thermal conductivity for coordinate transformation is obtained by filling nanoparticles into a substrate based on effective medium theory [9]. Guenneau et al. adopted coordinate transformation to thermodynamics and designed a multilayered thermal cloak consisting of homogeneous isotropic materials with realistic diffusivities [10].

The first experimental demonstration of thermal cloaking was shown by Narayana and Sato [12]. Multilayered composites are used to achieve thermal cloaking as well as thermal concentration and flux rotation in a steady-state condition. Figure 2(a) shows the multilayer-based thermal cloak with 40 alternating layers of latex rubber (material A, k_A = 0.13 W · m⁻¹K⁻¹) and silicone elastomers (material B, k_b = 2.6 W · m⁻¹K⁻¹). The host background material is agar-water block with k_hb = 0.56 W · m⁻¹K⁻¹ and $kh2 ∼kAkB$ is the key to achieve the least perturbation [12]. The steady-state temperature profile with a lateral temperature gradient is shown in Fig. 2(d). Dede et al. fabricated multilayer-based thermal cloak using a standard PCB manufacturing process [15]. Schittny et al. [13] and Ma et al. [14] experimentally realized transient thermal cloaks that allow real-time thermal protection to the object. The design of a Cu-based transient thermal cloak is shown in Fig. 2(b). The temperature profile with a lateral temperature gradient applied for 120 s is shown in Fig. 2(e), where the temperature in the cloaked region is smaller than its surroundings. However, in the long-time limit, a small amount of thermal energy will diffuse into the cloaked region due to the finite thermal conductivity of the insulating layers. The temperature of the cloaked region will eventually heat up and approach the steady-state temperature [13]. Han et al. established a general design method to create steady-state thermal cloaks by using only homogeneous and natural materials [11]. He and Wu designed an open cloak, in which the temperature of the cloaked object can be sharply reduced compared to the closed cloak when the window is located at the low-temperature side [31]. Coordinate transformation-based thermal cloaks commonly rely on parameter simplification or directional functions for anisotropic geometries. Han et al. demonstrated an omnidirectional thermal cloak that is derived directly from the conduction equation without approximation [48]. The elliptical thermal cloak is shown in Fig. 2(c). The thermal cloak works along arbitrary directions of heat flow and its performance is validated in the time-dependent case as shown in Fig. 2(f) (temperature profile at t = 5 min). Moreover, a thermal cloak sensor, which is capable of cloaking itself and receiving the incoming signal simultaneously can also be achieved.

Another approach to construct a thermal cloak is scattering cancelation as discussed by Alu and Engheta to apply metamaterials for reducing the total scattering cross section of spherical and cylindrical objects [70]. The bilayer thermal cloak consists of two concentric shells, the inner layer is a thermal insulator to block heat flux from entering the object, and the outer layer minimizes the temperature distortion introduced by the inner layer. This technique was further developed in the experimental realization of a bilayer thermal cloak with only homogeneous and isotropic materials in 2D [17] and 3D [18] scenarios, as shown in Figs. 3(a), 3(b), 3(d), and 3(e). In addition to thermal cloaking, Ma et al. experimentally demonstrated an electric-thermal bifunctional cloak based on the same method [16].

Yet another strategy in constructing thermal cloaks for steady-state heat conduction is to use gradient-based homogenization design and optimization. Here, a thermal composite may be designed by representing the explicit heterogeneous microstructure of the composite via homogenized effective anisotropic material properties. In such a way, an optimization objective function is defined, and a gradient-based optimizer is exploited in minimizing the functional through the local design of the anisotropic material thermal-conductivity layout. This method was first proposed for thermal-composites by Dede [19] and then extended by Dede et al. [20], where optimal thermal composite annular structures were independently designed to realize effective heat flux cloaking, focusing, or reversal/guiding devices. The benefit of this numerical method is that it is highly geometrically flexible and can be applied to the design of arbitrarily shaped thermal metamaterials, as explained in Ref. [20]. Such material optimization techniques have been further applied by Fachinotti et al. [71] in the fabrication of anisotropic heat flux manipulation devices. Additionally, following He and Wu [39], the material design optimization technique has been employed in Ref. [40] for the useful design of “open” (i.e., cold side open) thermal cloaks for temperature-sensitive device cloaking or shielding in multilayer PCBs.

Despite this progress, in practice, the capability of the thermal metamaterial is limited because of the narrow range of thermal conductivities in natural solid materials, which ranges about four orders of magnitude from 0.1 to 1000 W · m⁻¹K⁻¹ at room temperature [72]. For thermal cloak designs based on coordinate transformation, scattering cancelation, or gradient-based design optimization methods, the thermal conductivity of the conductive or inner layers needs to be much larger than that of the background substrate. To minimize the perturbation of the heat flux at the interface with the background, the metamaterial-based composite needs to be embedded in a background corresponding to the geometric mean of the thermal conductivities of the metamaterials' constituents [73]. Consequently, most of the thermal cloaks cannot operate when the background substrate is a high-thermal-conductivity material, e.g., Li et al. designed a thermal cloak that works in high-thermal-conductivity-backgrounds [74]. They identified an equivalence between zero index in Maxwell's equation and infinite thermal conductivity in Fourier's law and theoretically proved that the integrated high-speed fluid field is equivalent to a material with an infinitely large thermal conductivity. A near thermal zero-index cloak is constructed with a solid conductor embedded with circulating fluid as shown in Fig. 3(c). Their thermal cloak works with Cu as the background material and acts as a transient temperature sensor as the temperature of the object follows the environmental changes as shown in Fig. 3(f).

With the trend toward high packaging density of electronics, it becomes severely important to dissipate heat in a well-defined path to reduce thermal crosstalk between adjacent devices and protect thermally sensitive components. While an extensive number of fundamental studies about thermal metamaterials have shown heat flow manipulation, the ideal thermal metamaterials are usually composed of curved lines or complex structures that are costly to fabricate [75]. On the other hand, thermal shifters composed of two isotropic materials have shown the ability to bend heat flux on demand with good manufacturability [66,76]. Considering two alternatively stacked isotropic materials with thermal conductivities of k₁ and k₂ as shown in Fig. 4(a). The heat flux rotation is a function of the composite layer orientation. Assuming material 1 is Cu (k₁ = 390 W · m⁻¹K⁻¹) and material 2 is stainless steel (k₂ = 42 W · m⁻¹K⁻¹), the heat flux can be bended upward by 26 deg when composite layer orientation θ = 45 deg; see Fig. 4(b) [66]. Figure 4(c) shows the relationship between heat flux rotation, thermal-conductivity ratio of two materials, and the rotation angle of the composite. A large thermal-conductivity ratio leads to a large heat flux rotation [76].

The thermal shifter could be used as a unit cell to enable multifunctional thermal metamaterials such as a thermal cloak, concentrator, etc. [75,77]. Figure 5(a) shows the design of a tunable thermal cloak by the diverse assembly of 4 × 4 thermal shifters with orientations of $±$15 deg, $±$45 deg, and $±$75 deg. The thermal shifter unit cell was composited of Cu and PDMS; see Fig. 5(b). Figure 5(c) shows that the thermal shield has a reduced temperature gradient in the center when subject to a lateral temperature gradient. Kang et al. reported a temperature-responsive thermal cloak that can induce dynamic changes in thermal energy distribution by integrating phase-change materials (PCMs) [33]. The thermal cloak was constructed by 4 × 4 thermal shifters with a similar design as shown in Fig. 5(a). The two materials are stainless steel and n-octadecane filled with multiwalled carbon nanotube (MWCNTs) and Cu power, which is used as the phase-change nanocomposite (PCNC) to provide a modulation of thermal conductivity with respect to ambient temperature; see Fig. 5(d). The transition temperature of PCNC is 28 °C, and the thermal conductivity of PCNC is 5.0 and 0.75 W · m⁻¹K⁻¹ at 20 and 35 °C, respectively. Figures 5(e) and 5(f) show the temperature profiles of the thermal cloak at low and high ambient temperatures with respect to a lateral temperature gradient. At a low-temperature range of 20–24 °C, PCNC is in the solid-state phase and has a comparable thermal conductivity to stainless steel, the thermal cloaking is at off-mode. On the contrary, at a high-temperature range of 30–41 °C, PCNC transforms into a liquid phase state and with a much lower thermal conductivity, which acts as a thermal insulator and protects the cloaked region (thermal cloaking at on-mode). The temperature responsive thermal cloak can be potentially applied to protect temperature-sensitive devices through related isolation as well as dissipation.

Thermal management has long been considered as one of the keys to maximize device performance and reliability. Compared to conventional MCPs (multichip packages) and sip (system in package), advanced heterogeneous packages face more challenges in thermal management due to the targeted finer pitches, 3D stacks, more inputs/outputs (I/Os), higher densities, higher power consumptions, and higher performance applications [78–81].

Thermal management challenges in heterogeneous packages can be understood from two points of view. First, high-performance chips are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different. This is a common scenario in 2.5D package platforms [28,46,79,82–93]. Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips. This is a common scenario in 3D package platforms such as TSV-sip (through silicon via) and HBM [94–103]. These two categories of thermal management challenges are reviewed in Secs. 3.1 and 3.2.

In 2.5D package platforms, chips can be located in one interposer, regardless of which node process they are, to achieve enhanced performance, lower tolerance, and higher power efficiency, which are required for heterogeneous packages to achieve a minimal footprint. To minimize the package area, high power chips are located as close as possible. In this section, the details of thermal management challenges in side-by-side multichip implementations are reviewed with discussions of high power density requirements, thermal crosstalk, varying temperature criteria, thermal interface materials (TIMs), and substrate thermal resistance.

Thermal management challenge is mostly driven by the continuous increase in power density. Many of the 2.5D package platforms use a silicon interposer to interconnect logic chips and HBMs [78–80,88,93], which have a high heat flux more than 100 W · cm⁻² in a single package [81,104,105]. This requires effective cooling very close to the heat source. However, some of the 2.5D packages have various layers, such as TIM and heat slug layers, between the heat source and the heat sink for reliability concerns at the board level [83,85,89,92]. When the heat sink has a rough contact surface and the 2.5D package has a large thermally induced or assembly warpage, the possibility of the active device cracking and failure increases after the heat sink is attached. Heat slugs and a TIM layer can be used to reduce the possibility of having a device crack for 2.5D packages but increases the thermal resistance between the heat sink and heat source. In the same time, the logic power is continuously increased with higher stacked HBMs for meeting performance requirements [27,28]. According to the international technology roadmap for semiconductors [106], the power density of the microprocessor has increased from about 40 W · cm⁻² (in the present day) to about 100 W · cm⁻² (in 2020). A high efficient cooling solution is needed at the system level to address the increased number of hot spots in a single package. The system-level solution refers to cooling with the casing and other systems, and the board-level solution refers to cooling without the casing. Thermal metamaterials may provide a better path for cooling through controlled heat flux transfer in the latter case.

In advanced heterogeneous packages, heat generation in each device can affect neighboring units [28,46,78,81,83,107]. In the 2.5D package platform, the logic device and HBMs are placed within 500 μm because of signal integrity/power integrity (SI/PI) performance. Thermal crosstalk could have detrimental effects, such as an increase in leakage power [108]; see Fig. 6. In general, for logic devices whose current leakage significantly increases with temperature, heat generation from adjacent devices leads to increased current leakage, which could aggravate the self-heating and increase the temperature. To reduce the thermal crosstalk, the distance between the individual logic chips could be increased, a low-thermal-conductivity material mold could be employed to create a thermal barrier between the devices, or a thermal metamaterial design could be implemented to realize a thermal channel running from hot spots to heat sink.

In general, each device has a maximum operation temperature, such as 125 °C for a logic chip and 85 °C for a memory chip [29,30], that affects the reliability of operation [28,30,46,84,109]. These temperatures are considered as upper limits for reliable operations and performance and should not be exceeded. However, if devices with different operational temperature limits are placed adjacent to each other such as in 2.5D package platforms, the chip of a lower operation temperature limit could easily exceed the limitation due to the thermal crosstalk from a higher operating temperature chip. Also, the logic chip power is normally higher than that of the memory chip when they operate for high performance, which causes a significant thermal crosstalk from logic to memory. This thermal crosstalk effect can be observed from a power envelop graph.

Figure 7 shows the power envelop graphs for ipop (interposer package on package) and FO-sip (fan-out system in package) package platforms [28]. The inflection point is observed due to different maximum operation temperature limits of logic and memory chips. From the power envelope graph, the graph area can be considered as a metric scope of performance or efficiency and better thermal performance package shows larger power envelope area. Figure 7 shows that the FO-sip's power envelope area is larger than ipop's power envelop area, which means the fo-sip is a thermally enhanced platform compared with ipop. With the optimal thermal management solution, the logic chip and HBM could be placed closely with the maximum performance and operating temperatures close to 125 °C and 95 °C, respectively, and the power envelope area would be increased as shown in Fig. 7.

Thermal interface materials are generally used between active devices and a cooling system, whose performance is related to the thermal conductivity and the bond layer thickness (BLT) [110–112]. High-thermal conductivity and low BLT are preferred for thermal management [113–115]. In 2.5D package platforms, TIMs are typically used on ASIC (application-specific) and HBM [85]. ASIC and HBM have different thermomechanical properties, because ASICs are made of a single chip, and HBMs are made of several chips with multilevel vertical stacks. Even with the same applied pressure, HBM is more vulnerable to mechanical stresses. For this reason, when the same TIM is applied on ASIC and HBM, the BLT is likely to be limited by the HBM's mechanical reliability. When the BLT is fixed, different TIMs could be used on each individual device to maximize the performance. Alternatively, the height of the devices could be modified to the TIM's compression characteristics for the heterogenous package [116], as shown in Fig. 8. In addition, due to the large size of the substrate, the TIM's performance is degraded by voiding, pumping out, and drying out by warpage depending on the operational temperature change. Material selection is facilitated through power thermal cycle inspection of the selected TIM to identify the least impact on performance degradation. Considering that metamaterials make use of an effective thermal medium approximation, the related design principles may be used to controllably fabricate a multilayer TIM.

For the advanced heterogenous package, multiple devices are placed on one substrate and thus the number of signal I/Os and power I/Os tend to increase the effective substrate thickness [80,81,117]. When substrates become thicker, the vertical thermal resistance is increased by the number of substrate dielectric layers that nominally have low-thermal conductivity. A thick substrate is one of the main thermal challenges for 2.5D integration. Thermal metamaterials can be considered to enhance heat transfer through the substrate, when integrated with interposer design, and other thermal solutions such as the thermal via, a metal core, and metal block solutions may also be considered.

Similar to 2.5D package platforms, 3D package platforms are designed to implement heterogeneous integration with a minimal footprint while providing advantages in lowering latency, reducing power consumption, and increasing interconnect bandwidth. With 3D interconnections, the stacked chips create complex thermal management challenges. In this section, the details of thermal management challenges and solutions are reviewed including heat removal through stacked chips, thermal resistance by joint layers, limited thermal spreading by thinned chips, and TSV solutions.

In 3D chip stacks, the hottest die is the one closest to the substrate due to I/O count or S/I and P/I performance reasons. The heat from the hottest chip is dissipated through the stacked devices, which causes challenges for thermal management because each stacked chip works as a thermal resistance, and the heat from the hottest chip affects the other chips; see Fig. 9. The hottest device should be located close to the cooling system or should have a direct heat path from the hottest chip to the cooling system to enhance cooling efficiency. Aditya et al. [118] shows that the thermal advantages in the TSV-sip package platform.

In the 3D stack platform, chip bonding is the main factor for increasing the vertical thermal resistance [100,102,119,120]. A 3D stack joint layer consists of microbumps and a nonconductive film (NCF). A microbump's thermal conductivity is about 60 W · m⁻¹K⁻¹ and the NCF thermal conductivity is about 0.5 W · m⁻¹K⁻¹, both of which are significantly lower than Si thermal conductivity of about 120 W · m⁻¹K⁻¹. So, both features contribute to dramatically increase the vertical thermal resistance. In addition, the chip back end of line layer has lower thermal conductivity than Si [121–123], which also contributes to increase the vertical thermal resistance. Moreover, the interface thermal contact resistance in the junction also contributes. Because of these reasons, the vertical thermal resistance increases rapidly with the number of interconnection layers as shown in Fig. 10.

If there is no limit to the package thickness, the chip thickness can be as thick as possible to increase the heat spreading of the hot spot inside the chip [124]. However, the package thickness is usually constrained by system design which affects the 3D stacked device height. In particular, for interconnection using TSVs, the chip thickness is restricted due to a design limitation of the TSV [125]. A chip thickness with TSVs can be much lower than the maximum thickness allowed for single-chips without TSVs (about 780 μm) [126], which can lead to limited lateral heat spreading or increased lateral thermal resistance.

The TSV count, location, dimension, and thermal properties are considered as design parameters to enhance TSV heat transfer. Moreover, when the locations of TSVs are well aligned with other stacked chips, this could work as a thermal path from the heat source to the heat sink [38,127–134]. For example, thermal TSVs (TTSVs), either integrated with thermal metamaterials or designed using metamaterial principles, can be placed close to hot spot regions to facilitate enhanced heat dissipation in 3D ICs [135], following the principle laid out in Sec. 2.1. However, for the complicated 3D connection, the placement of thermal TSV can be one of the design challenges. The area near the hot spot is a very “popular zone” to enhance SI/PI and thermal performance. To get the maximum performance of the nonhomogeneous 3D connection, the thermal TSV placement should be considered in SI/PI design as well.

When the stacked devices have different floorplans from each other, the signal/power TSVs are not located at the same position. In this case, thermal-aware floorplanning technologies, integrated with metamaterial elements and architectures can be used. Thermally aware floorplanning techniques can be categorized into TTSV insertion-based floor planning, force-directed technique-based floor planning, metaheuristic-based floor planning, and other floor planning methods [136]. From a package structure perspective, TTSV insertion-based floorplanning is a useful solution, as shown in Fig. 11. Many TTSV insertion-based floor planning studies had focused on an optimization method to reduce the number of TTSVs to keep peak temperature below the temperature criteria [34,36,37,39,40]. When the area and size of the 3D stacked devices are not the same, the smaller chip works as a heat path and the remaining area of the chip works as a thermal bottleneck. So, it is necessary to optimize the chip position or create an additional thermal channel, which may be achieved through a metamaterial with high contrast in the individual layer thermal conductivity as outlined in Sec. 2.3.

Advanced electronic devices have been increasingly demanded to have integration of more functions into individual chips. This has resulted in high-density packaging of electronics. Moreover, device and interconnect scaling dramatically affect the design and architecture of advanced assembly and packaging of electronics. Over the recent decade, power density associated with this scaling has been increasing because of increase in power dissipation and scaling down of the effective die area. It is also expected that power density will steadily increase for next-generation devices to beyond 1 kW · cm⁻² [137,138]. High heat fluxes on the components due to increase in power density create many challenges such as electromigration, material creep, thermal cycling, warpage; thus, thermal design and architecture considerations need to effectively keep the temperature under control to ensure reliable operation of electronics. Typical dies have different regions such as core, cache, so there are nonuniform power densities associated with these regions; thus, local heat fluxes can exceed 100 W · cm⁻². Cloaking and related thermal control applications, facilitated through metamaterial architectures (see Sec. 2.2), may be particularly useful in this regard for thermally sensitive device protection on the die.

Traditional cooling techniques have limitations on removing these localized high-power densities ∼100 W · cm⁻². Air cooling which is either active or passive has been one of the most commonly used traditional cooling techniques due to availability, simplicity, and capability to cool less than ∼250 W power dissipation [139]. Heat spreaders, heat sinks with or without heat pipes are typical examples used in concert with air cooling. In passive air cooling, natural convection, conduction, and radiation heat transfer can cool the electronic components/devices via heat spreaders or heat sinks. Up to ∼10 W could be cooled by passive air cooling [140]. This type of cooling is useful for small electronic devices that have lower power. In active air cooling, external components such as a fan or blower circulate air over the electronics. In general, multiple fans or blowers with different configurations are designed to cool the high-density microelectronic packages. There are also some challenges mainly on the fans or blowers; for instance, higher rotational speeds result in higher noise which is also restricted by the acoustic limit of the system environment, and faster fatigue. Furthermore, heat sink design, TIM selection, and overall mechanical assembly of components create reliability concerns. Single-phase liquid cooling has long been applied when power dissipation within the electronic component exceeds ∼250 W and when traditional air-cooling thermal management is insufficient enough to cool below a thermal design point [41,141,142]. Two-phase liquid cooling, jet impingement, liquid–vapor phase change, immersion cooling, and direct liquid cooling are some of the other cooling techniques that have been continuously researched and developed for various electronic applications to cool up to ∼600 W · cm⁻² [42]. However, cost, leakage, and pressure drop within the system create concerns and limitations. Thus, the acceptance of liquid cooling varies for different industries.

System-level packaging and thermal cooling are also challenged by high power components within a limited space. For instance, IBM recently designed the fastest supercomputer in the world [143] that has six graphics processing units (GPUs) having 300 W thermal design power, and two central processing units (CPUs) having 250 W thermal design power, which is illustrated in Fig. 12. This system has two parallel paths where water is used as a liquid cooling to cool the high-power components (GPUs and CPUs) and forced air cooling is applied for the other low power components in the system. The evenly split flow cools CPU and 3 GPU modules that are connected via cold plate assembly in each path. The cold plate assembly is flexible and can accommodate the expected height range of GPUs. Energy efficient data center design was also considered and implemented.

The total power in the supercomputer is continuously increasing and exceeding ∼3 kW. Moreover, the typical server size installed into the racks is 2 U (∼88.9 mm) high, 483 mm wide, and 711 mm deep, which makes the power density in the system high. Also, preheat is a main concern for the back section of the supercomputers in only forced air-cooled systems as there are some components such as I/O or OpenCapi cards that require high-thermal cooling. Due to the wiring and motherboard design constraints, design and architecture of these cards are not quite flexible which affects the cooling power of such cards. In today's market, each card dissipates ∼40 W with quad small form-factor pluggable optical transceivers. The high-power generation is very challenging for only forced air-cooled system especially with dramatically increasing field programable gate arrays powers due to the preheating [144]. Thus, with on-chip hot spot heat fluxes approaching ∼1 kW · cm⁻² and high-power servers exceeding ∼3 kW, next-generation thermal cooling techniques are crucial to address the challenges and current limitations [145].

Similar device-to-package-to-system thermal challenges arise for next-generation power electronics and sensors found in highly automated and electrified vehicles. From a power electronics perspective, single- or two-phase remote (i.e., power package separated from cold plate) cooling strategies have been extensively investigated at the package level [146], and new near-junction cooling solutions [43,44] are being actively explored for compact, highly integrated, and high-performance alternatives that may address power semiconductor heat fluxes approaching ∼1 kW · cm⁻². Here, TIM and thermal crosstalk issues may again be a concern as active gate drive components are eventually integrated into or placed close to the power package. Thermal routing for such gate drive components is already a challenge point [45], and higher levels of integration for future mobility solutions (e.g., in-wheel motors) will continue to require innovative heat flow control and anisotropic thermal routing in three-dimensions at multiple scales. Thermal metamaterial-related architectures may now be necessary to better regulate the path of heat transfer. In addition to microelectronics-related applications, advanced sensors, photonic components found in solid-state waveguide devices, such as ring resonators or thermal phase-shifters, may also benefit from the incorporation of effective thermal conduits facilitated through geometrically considered placement of meta-atom based materials (see Sec. 2.1) to reduce transient response time and required actuation power [147,148]. Furthermore, the integration of lasers on-chip for photonic sensing and processing solutions also presents a host of thermal challenges due to the proximity of the light source near other potentially thermally sensitive components [149]. Thus, highly local-scale application of thermal metamaterials as suggested by Loke et al. [150] is definite area for future exploration for a variety of device-to-package applications.

While thermal metamaterials with extraordinary properties are expected to be useful for thermal management applications [25], most of the work is limited to materials investigations and fundamental studies. There have been recent developments in using thermal metamaterials and taking advantage of heat flow control for electronic systems at the PCB-level [23] and with microelectromechanical systems [151]. Further investigations on the implementation of thermal metamaterials could address chip-integrated and package-level thermal management challenges. For example, for 2.5D packages, thermal metamaterials based on anisotropic material layouts for thermally cloaking, or isolating designs could be used to engineer heat dissipation in a deterministic manner and minimize thermal crosstalk between ASIC and HBM (Fig. 13). Optimal patterning of interposers, as well as TTSVs, could not only minimize thermal crosstalk but also limit the temperature increase of the ASIC. For 3D packages, thermal metamaterials based on bending or shifting designs could be used to guide the heat efficiently toward heat sinks and facilitate heat dissipation through HBM stacks. Thermal management of 3D stacks could be further addressed by optimal arrangements of TSVs and potential use of silicon-based thermoelectric cooling elements [34,36,37,39,59,61,132,136]. Several studies discussed the potential use of thermal metamaterials for circuit designs [15,19,20,152]. Their work demonstrated an optimal separation of a hot spot region and a temperature-sensitive device region using the thermal metamaterial design functions in one PCB. We can infer that thermal metamaterial designs can be applied to heterogeneous packages where multiple chips are used and multiple hot spots are expected.

While the progress and development of thermal metamaterials are promising for electronic packaging applications, direct implementation of those thermal metamaterial designs in current packaging systems will be very challenging, due to disruption of used process flows, and further studies on their effectiveness, compatibility, and scalability are necessary. Dede et al. [152] provides an example design of a synchronous buck converter utilizing the various aspects of thermal metamaterials. It also talks about the lacking electrothermal design methodologies that are needed for incorporation of thermal metamaterial designs. Evans et al. [153] demonstrates-power packaging design tools, in which the tool could be adapted to incorporate thermal metamaterial design into power electronics. Thus, electronics computer-aided design (ECAD) or multi-objective optimization tools relevant to different applications (e.g., Ref. [153] for power packaging, [154,155] for light-emitting diode packaging, and [156] for microserver design) could be modified to foster further integration of anisotropic heat spreaders or thermal metamaterials.

From a material perspective, thermal metamaterial designs would also benefit from advances in materials science research that push the limits of high-thermal conductivity, k_high, and low-thermal conductivity, k_low, materials since the thermal-conductivity contrast ratio, k_high/k_low, is critical in the establishment of effective designs. This ratio crucially affects both heat flow control and the overall device maximum temperature profile. Hence, advances in robust, reliable, and cost effective anisotropic thermal composite substrates beyond traditional PCBs and ceramic substrates that allow for easy implementation of high-thermal-conductivity contrast ratios are needed.

Practical implementation of PCMs into new substrate or carrier configurations is then another logical and challenging next-step opportunity to address transient response. Nonsolid-state PCMs have challenges associated with encapsulation, voiding, and long-term reliability [157]. However, as discussed in Sec. 2.3, utilization of these materials introduces new ways to actively manipulate heat flow paths. Thus, to ensure packaging viability, compatibility, and scalability, the choices of materials for thermal metamaterial designs needs to be carefully reviewed. To avoid potential thermal expansion and long-term interface issues, thermal metamaterial designs based on a homogeneous material may be preferred. Materials, with well-defined geometric structures, that are easily fabricated or manufactured would be additionally useful.

Moving beyond thermal metamaterials that are passively designed to manipulate directions of heat flow, future research on active thermal metamaterial devices such as thermal diodes, switches, or regulators could lead to new pathways of temperature control and dynamic thermal management for electronic packaging. The aforementioned PCMs fall into this category, as well, and may be leveraged likewise in temperature adaptive response.

Finally, we expect future research could take on system-level studies that focus on implementation of thermal metamaterials in high-performance heterogeneous packages as related to frontier, 5G-related communications, or photonics applications.

In this paper, we have reviewed the recent progress in conduction-based thermal metamaterials and considered their potential applications to electronic packaging. Such aspects indicate that basic research in thermal metamaterials can make a positive impact not only on the fundamental understanding of heat transfer but also on designs of next-generation electronics and photonics. As notable examples, 2.5D and 3D packages can suffer from nontrivial thermal management challenges such as thermal crosstalk and local hot spots, and associated packaging designs may benefit from the new capabilities of controlling heat transfer paths in a deterministic manner, underlying the scope and aim of thermal metamaterial design. We have reviewed thermal metamaterial approaches including: (1) anisotropic heat spreaders and diffusers, (2) heat cloaking and isolating, and (3) heat guiding and bending and provided a comprehensive overview of the related studies from the recent literature. We have analyzed the thermal challenges of advanced heterogeneous packaging from two points of view involving: (1) high-performance chips that are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different (via the 2.5D package platform); and (2) high-performance chips that are vertically stacked while the thermal resistance increases with the number of stacked chips (via the 3D package platform).

While significant attention in the electronic packaging community has been given to various thermal management techniques, conventional approaches are usually confined to an individual design scale such as the device, package, or system. Many prior solution techniques operate in isolation and may ultimately conflict with each other. We have discussed the outlook on applying thermal metamaterials for electronic applications, and metamaterial solutions could be used for thermal management at all of these scales. While a thermal metamaterial design may be a good heat transfer solution in of itself, further research and development into associated and required multidisciplinary electronic packaging methodologies may hold the key to synergy between thermal management techniques at multiple levels. This observation and analysis encourage new ECAD design tools, base material systems, and active devices as critical future research directions. Thus, in the future, research on thermal management may logically combine efforts across technical fields by leveraging the metamaterial concept.

The authors would like to thank Dr. Tae Hwan Kim, Dr. Young Hoon Hyun, and Dr. Bangwon Lee at Samsung Electronics for helpful discussions.

• Samsung Electronics and the National Science Foundation (CMMI-1902685) (Funder IDs: 10.13039/100004358 and 10.13039/100000001).

• National Science Foundation (CBET-1606192) (Funder ID: 10.13039/100000001).

I =

applied current

ipop =

interposer package on package

k_a-h =

thermal conductivity of region a-h of the perfect thermal diffuser

k_A =

thermal conductivity of material A

k_B =

thermal conductivity of material B

k_Cu =

thermal conductivity of copper

k_hb =

thermal conductivity of the host background material

k_high =

high-thermal conductivity

$kij$ =

second-order thermal-conductivity tensor

k_low =

low-thermal conductivity

k_PDMS =

thermal conductivity of PDMS

k_x, k_y =

in-plane thermal conductivity

k_z =

cross-plane thermal conductivity

k₁ =

thermal conductivity of material 1

k₂ =

thermal conductivity of material 2

$q″$=

input heat flux to the perfect thermal diffuser

$qi$ =

heat flux in the ith direction

sip =

system in package

t =

time

T₁ =

temperature applied to the chip

T₂ =

temperature applied to the spreader

θ =

composite layer orientation

ϕ =

heat flux bending angle

$∇Tj$ =

temperature gradient in the jth direction