The ubiquitous eutectic tin-lead (Sn–Pb) solder alloys are soon to be replaced with lead-free alternatives. In light of this transition, new computational tools for predicting the fatigue life of lead-free solders are required. A fatigue life prediction methodology was developed, based on stress-strain, creep, and isothermal fatigue data; the latter generated using a double lap-shear (DLS) test assembly. The proposed fatigue life prediction methodology builds on current practices in fatigue prediction for solder alloys, particularly the concepts of unpartitioned energy methods in finite element analysis (FEA) and continuum damage mechanics. As such, the current state of these fields is briefly discussed. Next, the global and local FEA simulations of the DLS test assembly are detailed. A correlation is then made between the empirical data and the FEA simulations. A general fatigue life prediction methodology is next described in detail. Finally, this methodology is tested and verified against the empirical data.
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March 2009
Research Papers
A General Methodology to Predict Fatigue Life in Lead-Free Solder Alloy Interconnects
David M. Pierce,
David M. Pierce
Department of Mechanical Engineering,
Stanford University
, Stanford, CA 94305
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Sheri D. Sheppard,
Sheri D. Sheppard
Department of Mechanical Engineering,
Stanford University
, Stanford, CA 94305
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Paul T. Vianco
Paul T. Vianco
Sandia National Laboratories
, Albuquerque, NM 87185
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David M. Pierce
Department of Mechanical Engineering,
Stanford University
, Stanford, CA 94305
Sheri D. Sheppard
Department of Mechanical Engineering,
Stanford University
, Stanford, CA 94305
Paul T. Vianco
Sandia National Laboratories
, Albuquerque, NM 87185J. Electron. Packag. Mar 2009, 131(1): 011008 (11 pages)
Published Online: February 13, 2009
Article history
Received:
August 8, 2007
Revised:
August 9, 2008
Published:
February 13, 2009
Citation
Pierce, D. M., Sheppard, S. D., and Vianco, P. T. (February 13, 2009). "A General Methodology to Predict Fatigue Life in Lead-Free Solder Alloy Interconnects." ASME. J. Electron. Packag. March 2009; 131(1): 011008. https://doi.org/10.1115/1.3068313
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