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Review Article

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

[+] Author and Article Information
John Lau

ASM Pacific Technology 852-2619-2757
john.lau@asmpt.com

1Corresponding author.

ASME doi:10.1115/1.4043341 History: Received October 19, 2018; Revised March 14, 2019

Abstract

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) LDI (laser direct imaging)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer vs. panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

Copyright (c) 2019 by ASME
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