Review Article

Structural Design of LGA Loading Mechanisms for Intel CPU Stack Retention

[+] Author and Article Information
Phil Geng

ASME fellow, Intel Corporation, 2111 NE 25th Avenue, Hillsboro, OR 97124

1Corresponding author.

ASME doi:10.1115/1.4042800 History: Received May 31, 2018; Revised December 24, 2018


For more than a decade, Land Grid Array (LGA) has been one of the main Central Processor Unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group.

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