Research Papers

A Wire-Bondless Packaging Platform for Silicon Carbide Power Semiconductor Devices

[+] Author and Article Information
Liang Yin

General Electric,
Global Research Center,
Niskayuna, NY 12309
e-mail: Liang.Yin@ge.com

Christopher Kapusta, Arun Gowda, Kaustubh Nagarkar

General Electric,
Global Research Center,
Niskayuna, NY 12309

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received October 22, 2017; final manuscript received June 3, 2018; published online July 2, 2018. Assoc. Editor: Satish Chaparala.

J. Electron. Packag 140(3), 031009 (Jul 02, 2018) (8 pages) Paper No: EP-17-1113; doi: 10.1115/1.4040499 History: Received October 22, 2017; Revised June 03, 2018

As silicon carbide (SiC) power semiconductor devices continue to mature for market adoption, innovative power electronics packaging designs and materials are needed. Wire-bonding loop is one of the limiting factors in traditional module packaging methods. Wire-bondless packaging methods have been demonstrated with low losses and to allow integration of gate drive circuit. In this paper, a wire-bondless packaging platform, referred to as power overlay kiloWatt (POL-kW), for SiC devices is presented. The packaging platform is intended for motor drives and power conversion in automotive, aerospace, and renewable power applications. POL-kW module's electrical and thermal performances are first summarized from previous experimental evaluations and numerical simulations. Although some of the evaluations were made using Si and Si–SiC hybrid modules, the results are applicable to SiC modules. Compared with aluminum wire-bonds, the utilization of polyimide-based Cu via interconnections resulted in much reduced parasitic inductance, contributing to significantly lower switching loss and less voltage overshoot. The POL-kW module with integrated heat sinks showed low thermal resistance, which was further reduced by double-sided cooling. Recent reliability results are presented, including high-temperature storage, temperature cycling, and power cycling.

Copyright © 2018 by ASME
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Elasser, A. , Chow, T. P. , and Chow , 2002, “ Silicon Carbide Benefits and Advantages for Power Electronics Circuits and Systems,” Proc. IEEE, 90(6), pp. 969–986. [CrossRef]
Neudeck, P. G. , Okojie, R. S. , and Chen, L. , 2002, “ High-Temperature Electronics—A Role for Wide Bandgap Semiconductors?,” Proc. IEEE, 90(6), pp. 1065–1076. [CrossRef]
Stevanovic, L. D. , Matocha, K. S. , Losee, P. A. , Glaser, J. S. , and Arthur, S. D., 2010, “ Recent Advances in Silicon Carbide MOSFET Power Devices,” 25th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Palm Springs, CA, Feb. 21–25, pp. 1603–1609.
Millán, J. , Godignon, P. , Perpiňà, X. , Pérez-Tomás, A. , and Rebollo, J. , 2014, “ A Survey of Wide Bandgap Power Semiconductor Devices,” IEEE Trans. Power Electron., 29(5), pp. 2155–2163. [CrossRef]
Horio, M. , Iizuka, Y. , Ikeda, Y. , Mochizuki, E. , and Takahashi, Y. , 2012, “ Ultra-Compact and High Reliable SiC MOSFET Power Module With 200C Operating Capability,” 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, Belgium, June 3–7, p. 81.
Scheuermann, U. , 2012, “ Reliability of Planar SKiN Interconnect Technology,” Seventh International Conference on Integrated Power Electronics Systems (CIPS), Nuremberg, Germany, Mar. 6–8, pp. 1–8. https://ieeexplore.ieee.org/abstract/document/6170666/
Weidner, K. , and Kaspar, M. , 2012, “ Planar Interconnect Technology for Power Module System Integration,” Seventh International Conference on Integrated Power Electronics Systems (CIPS), Nuremberg, Germany, Mar. 6–8, pp. 1–5. https://ieeexplore.ieee.org/document/6170665/
Seal, S. , Glover, M. D. , and Mantooth, H. A. , 2016, “ Flip-Chip Bonded SiC Power Devices on a Low Temperature Co-Fired Ceramic (LTCC) Substrate for Next Generation Power Modules,” IMAPS International Conference on High Temperature Electronics (HiTEC), Albuquerque, NM, May 10–12, pp. 159–168.
Liu, X. , Haque, S. , Wang, J. , and Lu, G. Q. , 2000, “ Packaging of Integrated Power Electronics Modules Using Flip-Chip Technology,” Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), New Orleans, LA, Feb. 6–10, pp. 290–296.
Xiao, Y. , Jain, N. P. , Barrett, J. , Rymaszewski, E. J. , Gutmann, R. J. , and Chow, T. P. , 2001, “ Flip-Chip Flex-Circuit Packaging for Power Electronics,” 13th International Symposium on Power Semiconductor Devices and ICs (ISPSD'01), Osaka, Japan, June 7, pp. 55–58.
Fisher, R. , Fillion, R. , Burgess, J. , and Hennessy, W. , 1995, “ High Frequency, Low Cost, Power Packaging Using Thin Film Power Overlay Technology,” Tenth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Dallas, TX, Mar. 5–9, pp. 12–17.
Gowda, A. , Tuominen, R. , and McConnelee, P. , 2014, “ Power Overlay (POL)—Advanced Embedding Packaging Technology Platform,” SMTA International Conference, Rosemont, IL, Sept. 28–Oct. 2.
Gowda, A. , McConnelee, P. , Tuominen, R. , Smith, S. , Hotaling, J., Zassowski, L., and Principe, L., 2014, “ Ultra-Thin Component Embedded Packaging Using Polyimide-Based Platform,” SMTA International Conference, Rosemont, IL, Sept. 28–Oct. 2.
Stevanovic, L. , Beaupre, R. , Delgado, E. , and Gowda, A. , 2010, “ Low Inductance Power Module With Blade Connector,” 25th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Palm Springs, CA, Feb. 21–25, pp. 1603–1609.
Pautsch, A. , Gowda, A. , Stevanovic, L. , and Beaupre, R. , 2009, “ Double-Sided Microchannel Cooling of a Power Electronics Module Using Power Overlay,” ASME Paper No. InterPACK2009-89190.
Stevanovic, L. , Beaupre, R. , Gowda, A. , Pautsch, A. , and Solovitz, S. , 2010, “ Integral Micro-Channel Liquid Cooling for Power Electronics,” 25th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Palm Springs, CA, Feb. 21–25, pp. 1591–1597.
Lutz, J. , Schlangenotto, H. , Scheuermann, U. D. , and Doncker, R. , 2011, Semiconductor Power Devices: Physics, Characteristics, Reliability, Springer, Berlin, Chap. 11. [CrossRef]
Ciappa, M. , 2002, “ Selected Failure Mechanisms of Modern Power Modules,” Microelectron. Reliab., 42(4–5), pp. 653–667. [CrossRef]
Seal, S. , and Mantooth, H. A. , 2017, “ High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions,” Energies, 10(3), p. 341. [CrossRef]
Yin, L. , Nagarkar, K. , Gowda, A. , Kapusta, C. , Tuominen, R. , Gillespie, P. , Sherman, D. , Johnson, T., Hayashibe, S., Ito, H., and Arai, T., 2017, “ Reliability of POL-kW Power Modules,” International Conference on Electronics Packaging (ICEP), Yamagata, Japan, Apr. 19–22, pp. 106–111.
Yin, L. , Nagarkar, K. , Kapusta, C. , Tuominen, R. , Gowda, A. , Hayashibe, S. , Ito, H. , and Arai, T. , 2017, “ POL-kW Modules for High Power Applications,” IEEE 67th Electronic Components and Technology Conference (ECTC), Orlando, FL, May 30–June 2, pp. 1497–1503.
Schulz-Harder, J. , 2003, “ Advantages and New Development of Direct Bonded Copper Substrates,” Microelectron. Reliab., 43(3), pp. 359–365. [CrossRef]
Herrmann, T. , Feller, M. , Lutz, J. , Bayerer, R. , and Licht, T. , 2007, “ Power Cycling Induced Failure Mechanisms in Solder Layers,” European Conference on Power Electronics and Applications, Aalborg, Denmark, Sept. 2–5, pp. 1–7.


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Fig. 1

Schematic of a typical POL-kW module structure in cross-sectional view. Copper vias are used as interconnects between dies (Al pads) and routings on the polyimide film surface. The adhesive layer is used to attach the dies to the polyimide film. Copper vias are formed by laser drilling and subsequently filling by electroplating. DBC substrate (Ni/Au finish) is soldered to the die backside metallization (Ag finish). An underfill is applied for electrical isolation and mechanical strengthening.

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Fig. 2

Typical POL-kW fabrication process flow

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Fig. 3

Wire-bonds versus POL-kW Cu via interconnects to power devices. Benefits of via interconnects include increased chip contact area and flexibility of via shape and size. The die size in the first two images was 7.4 mm by 7.4 mm. The wire-bond diameter was 0.5 mm. The POL via array had 25 vias with diameter of 0.75 mm. The die size in the right image was 4.5 mm by 2.25 mm.

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Fig. 4

A POL-kW submodule (a) top view (b) bottom view. The module is consisted of 24 SiC diode dies (2.5 mm by 2.5 mm) and 2 IGBT dies (14 mm by 11.5 mm). The Cu vias connect the top metallization (125 μm) on polyimide film to diode anode and IGBT emitter. Separate gate and emitter return traces are also present. The die backside metallization in the bottom view is diode cathode and IGBT collector [14].

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Fig. 5

Power overlay kiloWatt module after being assembled to ceramic substrate and an integrated heat sink. Connectors for power and gate were also attached [14].

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Fig. 6

Packaging parasitics was studied and compared on (a) wire bond module and (b) POL-kW module. The semiconductor devices and their placement in the two modules were identical. The devices used in the modules consisted of two 100 A 1200 V silicon IGBT chips (10.47 mm by 10.44 mm) and two 100 A 1200 V silicon diode chips (7.3 mm by 7.3 mm).

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Fig. 7

Electrical waveforms of wire-bond versus POL-kW modules. Both were rated as 300 A and 1200 V. The wire-bond module was a commercially off-the-shelf hybrid module and the POL-kW used identical IGBT dies and equivalent SiC dies. The double-pulse switching test was conducted at 300 A, 600 V, and 125 °C. The POL-kW module showed lower turn-on and turn-off losses, and lower voltage overshoot during turn-off. In addition, it had significantly less ringing of voltage and current during turn on [14].

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Fig. 8

Power overlay kiloWatt module with double-sided cooling: (a) A schematic of the cross section view of a POL-kW module with integrated top and bottom heat sinks and (b) a POL-kW module assembly with double-sided cooling [15]

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Fig. 9

Power overlay kiloWatt reliability test vehicle. The module consisted of 8 SiC diodes (1200 V 20 A), 6 daisy-chained via test chips and resistors. The vias on the diodes were 750 μm in diameter. The via on the test chips varied from 125 μm to 400 μm in diameter. The module size is 43 mm by 24.5 mm, and the total thickness is 1.7 mm [20].

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Fig. 10

Daisy-chained via test chips on the POL-kW reliability test module: (a) A chip with 200 μm vias and (b) A chip with 400 μm vias

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Fig. 11

Scanning electron microscopy micrographs showing the cross section views of a 750 μm diameter via after 500 cycles from −55 to 150 °C: (a) left end of the via and (b) right end of the via. No interfacial delamination and via cracking was detected.

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Fig. 12

Power cycling result of POL-kW module for 120 A current, with cycling intervals of 1 s ON and 1 s OFF. ΔTj = 90 °C (Tjmin ∼ 40 °C, Tjmax ∼ 130 °C). The junction temperature swing ΔTj and on-state voltage Von decreased initially and then were stable through 2 × 105 cycles.



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