Research Papers

Mixed Array of Compliant Interconnects to Balance Mechanical and Electrical Characteristics

[+] Author and Article Information
R. I. Okereke

Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
813 Ferst Drive,
Atlanta, GA 30332

S. K. Sitaraman

Fellow ASME
Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
813 Ferst Drive,
Atlanta, GA 30332

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 13, 2014; final manuscript received March 14, 2015; published online April 17, 2015. Assoc. Editor: Tong Cui.

J. Electron. Packag 137(3), 031006 (Sep 01, 2015) (9 pages) Paper No: EP-14-1030; doi: 10.1115/1.4030065 History: Received March 13, 2014; Revised March 14, 2015; Online April 17, 2015

Various designs of compliant interconnects are being pursued in universities and industry to accommodate the coefficient of thermal expansion (CTE) mismatch between die and substrate or substrate and board. Although such interconnects are able to mechanically decouple the components, electrical parasitics of compliant interconnects are often high compared to the electrical parasitics of solder bump or solder ball interconnects. This increase in electrical parasitics is due to the fact that compliant interconnects typically having longer path lengths and smaller cross-sectional areas to provide compliance, which in turn, increases their electrical parasitics. In this paper, we present a mixed array of compliant interconnects as a tradeoff between mechanical compliance and electrical parasitics. In the proposed implementation, the die area is subdivided into three regions where high compliance, medium-compliance, and low-compliance interconnect variants are situated in the outer, middle, and inner regions of the die, respectively. By introducing the low-compliance variants into the assembly, interconnects with greatly reduced electrical parasitics can be used as power/ground interconnects, while the high-compliance interconnects, situated near the die edges, can be used as signal interconnects. This paper demonstrates the implementation of this configuration and also presents the experimental characterization of such heterogeneous array of interconnects.

Copyright © 2015 by ASME
Your Session has timed out. Please sign back in to continue.


Sitaraman, S. K., and Kacker, K., 2009, “Mechanically Compliant I/O Interconnects and Packaging,” Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. S.Bakir and J. D.Meindl, eds., Artech House, Norwood, MA, Chap. 3.
Dudek, R., Walter, H., Doering, R., Michel, B., Meyer, T., Zapf, J., and Hedler, H., 2005, “Thermo-Mechanical Design for Reliability of WLPs With Compliant Interconnects,” 7th Electronic Packaging Technology Conference (EPTC 2005), Singapore, Dec. 7–9, pp. 328–334. [CrossRef]
Zhu, Q., Ma, L., and Sitaraman, S. K., 2004, “Development of G-Helix Structure as Off-Chip Interconnect,” ASME J. Electron. Packag., 126(2), pp. 237–246. [CrossRef]
Kacker, K., Sokol, T., and Sitaraman, S. K., 2007, “FlexConnects: A Cost-Effective Implementation of Compliant Chip-To-Substrate Interconnects,” 57th Electronic Components and Technology Conference (ECTC '07), Reno, NV, May 29–June 1, pp. 1678–1684. [CrossRef]
Yang, H. S., and Bakir, M. S., 2010, “3D Integration of CMOS and MEMS Using Mechanically Flexible Interconnects (MFI) and Through Silicon Vias (TSV),” 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1–4, pp. 822–828. [CrossRef]
Xu, P., Pfeiffenberger, A. H., Ellis, C. D., and Hamilton, M. C., 2014, “Fabrication and Characterization of Double Helix Structures for Compliant and Reworkable Electrical Interconnects,” J. Microelectromech. Syst., 23(5), pp. 1219–1227. [CrossRef]
Zhang, C., Yang, H. S., and Bakir, M. S., 2014, “Mechanically Flexible Interconnects (MFIs) With Highly Scalable Pitch,” J. Micromech. Microeng., 24(5), p. 055024. [CrossRef]
Okereke, R., and Sitaraman, S. K., 2013, “Three-Path Electroplated Copper Compliant Interconnects—Fabrication and Modeling Studies,” 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 28–31, pp. 129–135. [CrossRef]
Kacker, K., Sokol, T., Yun, W., Swaminathan, M., and Sitaraman, S. K., 2007, “A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance,” ASME J. Electron. Packag., 129(4), pp. 460–468. [CrossRef]
Kobeda, E., and Irene, E., 1986, “A Measurement of Intrinsic SiO2 Film Stress Resulting From Low Temperature Thermal Oxidation of Si,” J. Vac. Sci. Technol., B, 4(3), pp. 720–722. [CrossRef]
Michaelides, S., and Sitaraman, S. K., 1998, “Effect of Material and Geometry Parameters on the Thermo-Mechanical Reliability of Flip-Chip Assemblies,” Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM’98), Seattle, WA, May 27–30, pp. 193–200. [CrossRef]
Engelmaier, W., 1987, “Results of the IPC Copper Foil Ductility Round-Robin Study,” Testing of Metallic and Inorganic Coatings (STP947), ASTM, Philadelphia, PA, pp. 66–95. [CrossRef]
Prabhu, A. S., Barker, D. B., and Pecht, M. G., 1995, “A Thermo-Mechanical Fatigue Analysis of High Density Interconnect Vias,” ASME Adv. Electron. Packag., 10(1), pp. 187–216.
Pang, J. H., Low, T., Xiong, B., and Che, F., 2003, “Design for Reliability (DFR) Methodology for Electronic Packaging Assemblies,” 5th Electronics Packaging Technology Conference (EPTC 2003), Singapore, Dec. 10–12, pp. 470–478. [CrossRef]
Yeo, A., Lee, C., and Pang, J. H., 2006, “Flip Chip Solder Joint Reliability Analysis Using Viscoplastic and Elastic-Plastic-Creep Constitutive Models,” IEEE Trans. Compon. Packag. Technol., 29(2), pp. 355–363. [CrossRef]
Bakir, M. S., Reed, H. A., Thacker, H. D., Patel, C. S., Kohl, P. A., Martin, K. P., and Meindl, J. D., 2003, “Sea of Leads (SoL) Ultrahigh Density Wafer-Level Chip Input/Output Interconnections for Gigascale Integration (GSI),” IEEE Trans. Electron Devices, 50(10), pp. 2039–2048. [CrossRef]
Strickland, S., Hester, J., Gowan, A., Montgomery, R., Geist, D., Blanche, J., McGuire, G., and Nash, T., 2011, “Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits,” NASA Marshall Space Flight Center, Huntsville, AL, Report No. NASA/TM-2011-216463.
Cheng, B., De Bruyker, D., Chua, C., Sahasrabuddhe, K., Shubin, I., Cunningham, J. E., Luo, Y., Bohringer, K. F., Krishnamoorthy, A. V., and Chow, E. M.2009, “Microspring Characterization and Flip-Chip Assembly Reliability,” IEEE Trans. Comp., Pack. Manuf. Tech., 3(2), pp. 187–196. [CrossRef] [CrossRef]


Grahic Jump Location
Fig. 1

(a) Topographical layout of heterogeneous implementation and (b) mask design

Grahic Jump Location
Fig. 2

In-plane compliance (mm/N) as a function of beam dimensions in μm (legend shows different beam thickness values)

Grahic Jump Location
Fig. 3

Fatigue life (number of thermal cycles) as a function of beam dimensions in μm (legend shows different beam thickness values)

Grahic Jump Location
Fig. 4

Electrical resistance (mΩ) as a function of interconnect dimensions in μm (legend shows different beam thickness values)

Grahic Jump Location
Fig. 5

Inductance (pH) as a function of beam dimensions in μm (legend shows different beam thickness values)

Grahic Jump Location
Fig. 6

Strip model of heterogeneous interconnect layout (die hidden)

Grahic Jump Location
Fig. 7

First principal stress (MPa) in die at room temperature

Grahic Jump Location
Fig. 8

First principal die stresses and die warpage of a solder bump package

Grahic Jump Location
Fig. 9

Out-of-plane die nodal displacement (mm) at room temperature

Grahic Jump Location
Fig. 10

Elemental accumulated total strain range of the third stabilized thermal cycle

Grahic Jump Location
Fig. 15

Load versus displacement plot to determine out-of-plane compliance

Grahic Jump Location
Fig. 14

Captured image from four wire resistance measurement setup

Grahic Jump Location
Fig. 13

Fabricated interconnects

Grahic Jump Location
Fig. 12

Interconnect photomask layout for heterogeneous die

Grahic Jump Location
Fig. 11

Accumulated total strain range comparison in a heterogeneous array package



Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In