Research Papers

Thermal Cycling Study of Quilt Packaging

[+] Author and Article Information
M. Ashraf Khan

Visiting Assistant Professor
Electrical and Computer Engineering Department,
Jackson State University,
Jackson, MS 39217
e-mail: mkhan3@alumni.nd.edu

Quanling Zheng

Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: qzheng@nd.edu

David Kopp

Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: kopp.dave@gmail.com

Wayne Buckhanan

Assistant Professor
Department of Computer Science,
Pacific Union College,
One Angwin Avenue,
Angwin, CA 94508
e-mail: waynebuckhanan@alumni.nd.edu

Jason M. Kulick

Indiana Integrated Circuits, LLC,
South Bend, IN 46617
e-mail: jason.kulick@indianaic.com

Patrick Fay

Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: pfay@nd.edu

Alfred M. Kriman

Visiting Professor
Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: alfred.m.kriman.1@nd.edu

Gary H. Bernstein

Frank M. Freimann Professor
of Electrical Engineering
Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: bernstein.1@nd.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 30, 2014; final manuscript received November 23, 2014; published online January 19, 2015. Assoc. Editor: Yi-Shao Lai.

J. Electron. Packag 137(2), 021008 (Jun 01, 2015) (7 pages) Paper No: EP-14-1057; doi: 10.1115/1.4029245 History: Received May 30, 2014; Revised November 23, 2014; Online January 19, 2015

The continued progress of micro-electronics often requires functionality that is spread across multiple chips. This need has led to the development of a variety of alternative chip-packaging technologies that offer increased speed and bandwidth, with lower losses, in an increasing number of interchip interconnects. One recent alternative is quilt packaging® (QP), which has already shown promise from a performance perspective. The geometry of QP is essentially lateral: large numbers of ultrawide-bandwidth interchip interconnects (superconnects) are made directly by nodules fabricated along the edges of adjacent chips. Metallurgical bonding of the nodules creates a system in the form of a “quilt” of separately manufactured chips. This new interconnect geometry is subject to stresses that are different from more conventional schemes. For example, the thermal stress that causes fatigue and lead to failure in ball grid arrays is essentially shear stress, whereas the most critical stresses in QP are tensile and compressive. This paper describes studies of fatigue failure in QP, with attention to critical high-stress regions previously identified by finite-element modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 °C to 125 °C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focused-ion-beam cross-sectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.

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Grahic Jump Location
Fig. 6

SEM micrograph of two chips with nodules plated and joined by Sn. The two chips are labeled “chip #1” and “chip #2” with their related nodules, nodules #1 and #2. The Sn-joined region is indicated by the dashed rectangle. The nodules are 200 μm wide at the solder joint.

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Fig. 5

Cu nodule pairs to microwave superconnects for CPW, where G and S indicate nodules for ground and signal lines, respectively. (a) Ground nodules have one side tapered, and the signal nodule has two sides tapered. (b) Optical micrograph of a CPW QP system [6]. The middle region of reflowed Sn appears dark due to light scattering away from the lens.

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Fig. 4

Top view of nodules with flat and jigsaw-patterned faces. Upward in the figure represents outward from the chip for each nodule.

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Fig. 3

The left nodule of Fig. 2(b) apart from the substrate. Total length, depth, and width are indicated by l, h, and w, respectively. The four surfaces of the nodule (two visible) that are anchored in the substrate are insulated by an oxide layer, shown at back and side of the nodule. The thin tin layer faces away to the upper right.

Grahic Jump Location
Fig. 2

Nodules on two quilted chips. (a) Two adjacent, “quilted” chips (upper structures) on a layer of epoxy (lightly shaded) on a copper heat spreader on a chip carrier. Along the space between the two chips are multiple metal nodules that effect electrical connections between the chips. (b) A connected nodule pair (close-up of circled region in (a)).

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Fig. 1

Schematic presentation of a three-chip “quilt” embedded in a package lead frame. Here, three chips are interconnected by QP nodules of two different sizes (larger nodules connecting chip 1 to chips 2 and 3, and much smaller nodules between chips 2 and 3), as well as wire bonds from chips 1 and 2 to the package lead frame. (Figure by M. Padberg, courtesy of Indiana Integrated Circuits, LLC.)

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Fig. 7

Measured thermal cycling profile

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Fig. 8

Result of 500 thermal cycles on a nodule. (a) Before thermal cycling. (b) After 500 thermal cycles. (c) The nodule is rotated 90 deg ccw and tilted at 52 deg away from the viewer. The milled area is indicated by a dashed rectangle. (d) The critical area of the top metal layer is indicated by a circle. The electroplated copper shown is at the back of the nodule. The layer remains intact after 500 cycles.

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Fig. 9

Same views as Fig. 8 for a second nodule after 1000 thermal cycles

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Fig. 10

Result of thermal cycling of a quilted nodule pair (same as shown in Fig. 6) with both right-angle and oblique corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.

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Fig. 11

Effect of thermal cycling on a pair of quilted, 200 μm-wide nodules with only right-angle corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.



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