Research Papers

High-Efficiency Transient Temperature Calculations for Applications in Dynamic Thermal Management of Electronic Devices

[+] Author and Article Information
Maxat N. Touzelbaev

Eurasian National University,
Astana, Kazakhstan
e-mail: touzelbaev_mn@enu.kz

Josef Miler, Kenneth E. Goodson

Department of Mechanical Engineering,
Stanford University,
Stanford, CA 94305

Yizhang Yang

Apple Inc.
Cupertino, CA 95014

Gamal Refai-Ahmed

PreQual Technologies Corp.,
Markham, ON, Canada

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the Journal of Electronic Packaging. Manuscript received July 3, 2012; final manuscript received April 18, 2013; published online July 24, 2013. Assoc. Editor: Amy Fleischer.

J. Electron. Packag 135(3), 031001 (Jul 24, 2013) (8 pages) Paper No: EP-12-1066; doi: 10.1115/1.4024747 History: Received July 03, 2012; Revised April 18, 2013

The highly nonuniform transient power densities in modern semiconductor devices present difficult performance and reliability challenges for circuit components, multiple levels of interconnections and packaging, and adversely impact overall power efficiencies. Runtime temperature calculations would be beneficial to architectures with dynamic thermal management, which control hotspots by effectively optimizing regional power densities. Unfortunately, existing algorithms remain computationally prohibitive for integration within such systems. This work addresses these shortcomings by formulating an efficient method for fast calculations of temperature response in semiconductor devices under a time-dependent dissipation power. A device temperature is represented as output of an infinite-impulse response (IIR) multistage digital filter, processing a stream of sampled power data; this method effectively calculates temperatures by a fast numerical convolution of the sampled power with the modeled system's impulse response. Parameters such as a steady-state thermal resistance or its extension to a transient regime, a thermal transfer function, are typically used with the assumption of a linearity and time-invariance (LTI) to form a basis for device thermal characterization. These modeling tools and the time-discretized estimates of dissipated power make digital filtering a well-suited technique for a run-time temperature calculation. A recursive property of the proposed algorithm allows a highly efficient use of an available computational resource; also, the impact of all of the input power trace is retained when calculating a temperature trace. A network identification by deconvolution (NID) method is used to extract a time-constant spectrum of the device temperature response. We verify this network extraction procedure for a simple geometry with a closed-form solution. In the proposed technique, the amount of microprocessor clock cycles needed for each temperature evaluation remains fixed, which results in a linear relationship between the overall computation time and the number of temperature evaluations. This is in contrast to time-domain convolution, where the number of clock cycles needed for each evaluation increases as the time window expands. The linear dependence is similar to techniques based on FFT algorithms; in this work, however, use of z-transforms significantly decreases the amount of computations needed per temperature evaluation, in addition to much reduced memory requirements. Together, these two features result in vast improvements in computational throughput and allow implementations of sophisticated runtime dynamic thermal management algorithms for all high-power architectures and expand the application range to embedded platforms for use in a pervasive computing environment.

Copyright © 2013 by ASME
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Fig. 2

(a) Foster RC ladder and (b) Cauer RC ladder representations of thermal system.

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Fig. 1

Example of a network circuit model of a chip die on a heat spreader attached to a heat sink. This type of model [5] is not well-suited for runtime implementations due to a significant computational penalty.

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Fig. 7

Schematic of the chip geometry used for the numerical simulation and proposed modeling method.

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Fig. 8

Thermal modeling of chip-spreader geometry shown on Fig. 7. Compared are the results of simulations using commercial solver with the output of an IIR filter based on 11 stage ladder. The power step is at 100 W. The maximum transient errors are less than 0.4% of the steady state response.

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Fig. 3

Network identification by deconvolution (NID) using responses in time and frequency domains for one-dimensional conduction with a restricted geometry discussed in Sec. 3

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Fig. 4

An identification of system poles and its semi-infinite limit. Refer to Sec. 3 for more detail.

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Fig. 5

Transfer function identification. The exact transfer function is well-represented with a limited number of circuit stages using proposed method. Deviations occur at high frequencies depending on the number of latter stages.

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Fig. 6

Time step-size dependence. Technique demonstrates good accuracy with limited time-steps. Slight deviations are observed at very short timescales when using limited number of time-steps.

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Fig. 9

Comparison between direct time-domain, frequency-domain and IIR digital filter convolution calculations using extracted models from step response given in Fig. 8.

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Fig. 10

Comparison in computational efficiency of different methods for evaluation of convolution integrals. The recursive IIR digital filter is superior to other convolution techniques and is best-suited for run-time temperature calculations.



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