Technical Briefs

Experimental Analysis Model of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers

[+] Author and Article Information
Huy N. Phan, Dereje Agonafer

Department of Mechanical and Aerospace Engineering, University of Texas at Arlington, Arlington, TX

J. Electron. Packag 132(2), 024501 (Jun 23, 2010) (4 pages) doi:10.1115/1.4001831 History: Received January 16, 2010; Revised May 18, 2010; Published June 23, 2010; Online June 23, 2010

Presently, stack dice are used widely as low-power memory applications because thermal management of 3D architecture such as high-power processors inherits many thermal challenges. Inadequate thermal management of three-dimensional integrated circuits (3D-ICs) leads to reduction in performance, reliability, and ultimately system catastrophic failure. Heat dissipation of 3D systems is highly nonuniform and nonunidirectional due to many factors such as power architectures, transistors packing density, and real estate available on the chip. In this study, the development of an experimental model of an active cooling method to cool a 25 W stack-dice to approximately 13°C utilizing a multidimensional configured thermoelectric will be presented.

Copyright © 2010 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.



Grahic Jump Location
Figure 11

MHTS processor temperature as a function of air flow rates and TEM input power (1.3–230 W) for 25 W processor

Grahic Jump Location
Figure 10

Processor temperature as a function of air flow rates and TEM input power for 25 W processor (1D cooling with TEM)

Grahic Jump Location
Figure 9

Processor temperature as a function of air flow rates for 25 W processor

Grahic Jump Location
Figure 8

Air flow bench test setup

Grahic Jump Location
Figure 6

Unidirectional cascade thermoelectric cooling configuration

Grahic Jump Location
Figure 5

Motherboard for Intel® Pentium® 4 processor (courtesy of Gigabyte)

Grahic Jump Location
Figure 4

Low-power high-integration 3D-PCB-package (10×10×10 mm3)(3)

Grahic Jump Location
Figure 3

Conventional cooling methods applied to 3D-ICs

Grahic Jump Location
Figure 2

Different dice stacking configurations

Grahic Jump Location
Figure 1

(a) Passive processor cooling and (b) active processor cooling using thermoelectric cooler for conventional non-3D-IC processors



Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In