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RESEARCH PAPERS

# Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps

[+] Author and Article Information
Daijiao Wang

Mechanical Engineering Department, The University of Texas at Austin, 1 University Station C2200, ETC 5.160, Austin, TX 78712

Ronald L. Panton

Mechanical Engineering Department, The University of Texas at Austin, 1 University Station C2200, ETC 5.160, Austin, TX 78712rpanton@mail.utexas.edu

J. Electron. Packag 127(4), 440-445 (Jan 04, 2005) (6 pages) doi:10.1115/1.2070047 History: Received June 29, 2004; Revised January 04, 2005

## Abstract

Experiments were carried out to investigate the effect of reversing the heat flux direction during cooling on the formation of voids during the reflow process. Under different upward and downward solidification conditions, 480 high-lead $(90Pb∕8Sn∕2Ag)$ solder joints of flip-chip assemblies were processed. The solder samples were then microsectioned to determine the size and location of voids. The results show that reversing the flow direction during cooling has a significant effect on the final void formation. For the case of the melting direction from top (flip-chip side) to bottom (test board side), reversing the heat flux direction results in solidification direction from top to bottom. The percentage of defective bumps was found to be 28% and the volume of voids per defective bump was 1.5%. This is the best reflow methodology to minimize voids. Without reversing the heat flux the defective bumps were 80% with 4.0% void volume. In the case of solidification direction/melting direction from bottom to top, the percentage of defective bumps increases from 40% to 51%, accompanying a rise of the volume of voids from 3.0% to 3.7%.

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## Figures

Figure 1

Marangoni flow inside molten solder (a) heat flux direction from chip to substrate, (b) heat flux direction from substrate to chip

Figure 2

(a) Reflow time-temperature profile, (b) the temperature differential across the flip-chip-substrate assembly (heating from top and cooling from top)

Figure 3

(a) Reflow time-temperature profile, (b) the temperature differential across the flip-chip-substrate assembly (heating from bottom and cooling from bottom)

Figure 4

The illustration of void locations in a solder bump

Figure 5

Average number of voids per defective bump distributed by void size

Figure 6

Average void volume percentages by regions for heating from top and cooling from top

Figure 7

Average void volume percentages by regions for heating from bottom and cooling from bottom

Figure 8

Micrographs of a solder bump reflowed with melting and cooling directions from top to bottom, (a) the first cut, (b) the fourth cut, (c) the eighth cut (the first, fourth, and eighth cuts are the beginnings of the top, middle, and bottom layers, respectively)

Figure 9

Void volume as percentage of total void volume as distributed by size and region for heating from top, cooling from top

Figure 10

Void volume as percentage of total void volume as distributed by size and region for heating from bottom, cooling from bottom

Figure 11

Micrographs of a solder bump reflowed with melting and cooling directions from bottom to top, (a) the first cut, (b) the fourth cut, (c) the eighth cut (the first, fourth, and eighth cuts are the beginnings of the top, middle, and bottom layers, respectively)

## Errata

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