An Efficient Solution for Wire Sweep Analysis in IC Packaging

[+] Author and Article Information
Jerry Su, Sheng-Jye Hwang

Department of Mechanical Engineering, National Cheng Kung University, Tainan, Taiwan

Francis Su, Shou-Kang Chen


J. Electron. Packag 125(1), 139-143 (Mar 14, 2003) (5 pages) doi:10.1115/1.1535447 History: Received April 12, 2002; Online March 14, 2003
Copyright © 2003 by ASME
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Han, S., 1994. “A Study on Plastic Encapsulation of Semiconductor Chips,” Cornell Injection Molding Program Technical Report No. 77.
Han, S., and Wang, K. K., 1993. “Analysis of Wire Sweep Related to Encapsulation of Semiconductor Chips,” Chap. X, CIMP Progress Report No. 17.
Han, S., and Wang, K. K., 1993. “A Study on the Effects of Fillers on Wire Sweep Related to Semiconductor Chip Encapsulation,” ASME Winter Annual Meeting.
Han, S., and Wang, K. K., 1995. “Flow Analysis in a Cavity with Leadframe during Semiconductor Chip Encapsulation,” Advances in Electronic Packaging ASME EEP-Vol. 10-1 .
C-MOLD Reactive Molding and Microchip Encapsulation Training Guide, C-MOLD Pacific.
Idelchik, I. E., 1994, Handbook of Hydraulic Resistance, CRC Press.


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Flow charts for wire sweep analysis provided by C-MOLD Microchip Encapsulation Solution and InPack (Gray icons represent the analysis method used in this paper)
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Coordinate system used in Lamb’s model
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User interface of InPack
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Detailed job functions and process flow of InPack
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Chip and leadframe assembly of TSOP II 40/44L package (epoxy flows from left to right, number beside the wire indicates the wire number)
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Wire sweep X-ray photo of TSOP II 40/44L package
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Averaged experimental measured wire sweep index of TSOP II 40/44L package
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Combine comparison of calculated results versus measured values for TSOP II 40/44L package
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Simulated wire sweep in graphic presentation for TSOP II 40/44L package (magnified at a scale of 10)



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