Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

[+] Author and Article Information
Y. T. Lin, C. T. Peng, K. N. Chiang

Dept. of Power Mechanical Engineering, National Tsing Hua University, HsinChu 30013, Taiwan

J. Electron. Packag 124(3), 234-239 (Jul 26, 2002) (6 pages) doi:10.1115/1.1481368 History: Received April 03, 2001; Online July 26, 2002
Copyright © 2002 by ASME
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Wire interconnect technology (source: Fujitsu)
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Top and cross-section view of conventional flip-chip BGA package without underfill layer
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Stress/strain curve of 60Sn/40Pb eutectic solder
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One-half finite element model of flip-chip BGA package
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Flip chip without underfill Laser Moiré phase diagram and refined fringe
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Half FEM Model of WIT wafer level package with 4, 5 and 7 column posts
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Half FEM model of conventional wafer level package with 4 solder bumps
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Illustrations of FEM models of parametric study
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Stress/strain curve of polyimide
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Accumulated equivalent plastic strain versus cycling time of conventional WLP
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Accumulated equivalent plastic strain versus cycling time of WIT Model 1
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Max. strain of outmost column post of WIT Model 2



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