Failure Estimation of Semiconductor Chip During Wire Bonding Process

[+] Author and Article Information
T. Ikeda, N. Miyazaki, K. Kudo

Department of Materials Process Engineering, Graduate School of Engineering, Kyushu University, Fukuoka 812-8581, Japan

K. Arita, H. Yakiyama

Kyushu Matsushita Electric Co., Ltd., Fukuoka 812-8531, Japan

J. Electron. Packag 121(2), 85-91 (Jun 01, 1999) (7 pages) doi:10.1115/1.2792672 History: Received November 13, 1995; Revised February 10, 1999; Online November 05, 2007


Wire bonding, a process of the connection between a semiconductor chip and a lead frame by a thin metal wire, is one of the important processes of electronic packaging. This paper presents failure estimation of a silicon chip and a GaAS chip during a gold wire bonding process. The gold wire bonding process is carried out by pressing a gold ball made at a tip of the gold wire on a semiconductor chip and vibrating it by ultrasonic. High contact pressure is useful for shortening the process cycle, but it sometimes causes failure of the semiconductor chip. Elastic-plastic large deformation contact analyses are performed and the distributions of the stresses in these semiconductor chips are investigated. The possibility of failure of a semiconductor chip under usual wire bonding pressure is pointed out only for a GaAs chip.

Copyright © 1999 by The American Society of Mechanical Engineers
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