Packaging Architecture Considerations of High Density Multi-Chip Electronic Packages Via System Optimization

[+] Author and Article Information
J. P. Krusius

School of Electrical Engineering, Cornell University, Ithaca, N.Y. 14853-5401

J. Electron. Packag 112(3), 267-271 (Sep 01, 1990) (5 pages) doi:10.1115/1.2904377 History: Received September 01, 1989; Revised June 12, 1990; Online April 28, 2008


Multi-chip packaging of high density CMOS based systems is analyzed using package system simulation, a new systematic methodology for design and trade-off studies of electronic packages in order to examine future trends. Technology parameters for a representative CMOS chip, multi-chip package (MCP), and printed wiring board technology are defined. Six key MCP parameters are optimized using simulated annealing. A large number of different optimum MCP’s for minimum system cycle time have been found. Based on this set key packaging parameter relationships are derived and associated future trends discussed. Finally, the significance of these trends to mechanical engineers is outlined.

Copyright © 1990 by The American Society of Mechanical Engineers
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