Approximating the Steiner Tree in the Placement Process

[+] Author and Article Information
Yeun Tsun Wong, Michael Pecht

Mechanical Engineering Department, University of Maryland, College Park, MD. 12783

J. Electron. Packag 111(3), 228-235 (Sep 01, 1989) (8 pages) doi:10.1115/1.3226538 History: Received October 26, 1988; Revised June 09, 1989; Online November 09, 2009


By simulating the movement of a node in a tree, an iso-distance error graph (IDEG) which contains connection errors generated by replacing a Steiner tree with its equivalent non-Steiner tree is developed. The IDEG is used to estimate how well various types of non-Steiner trees function as a Steiner tree in the placement of components on a printed wiring board (PWB). To reduce connection errors in the IDEG and pursue computational efficiency, a row-based tree family in which the tree length is primarily dependent on the terminal coordinates of each row, is constructed. Then, based on the analysis of the error distribution on the IDEG, the row-based trees and the spanning tree are compared in terms of their approximation to the Steiner tree.

Copyright © 1989 by ASME
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