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Review Article

J. Electron. Packag. 2019;141(4):040801-040801-27. doi:10.1115/1.4043341.

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(4):040802-040802-13. doi:10.1115/1.4043405.
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Fatigue failure of solder joints is one of the major causes of failure in electronic devices. Fatigue life prediction models of solder joints were first put forward in the early 1960s, and since then, numbers of methods were used to model the fatigue mechanism of solder joints. In this article, the majority fatigue life models are summarized, with emphasis on the latest developments in the fatigue life prediction methods. All the models reviewed are grouped into four categories based on the factors affecting the fatigue life of solder joints, which are: plastic strain-based fatigue models, creep damage-based fatigue models, energy-based fatigue models, and damage accumulation-based fatigue models. The models that do not fit any of the above categories are grouped into “other models.” Applications and potential limitations for those models are also discussed.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2019;141(4):041001-041001-13. doi:10.1115/1.4043406.

With recent advances in the state-of-the-art of power electronic devices, packaging has become one of the critical factors limiting the performance and durability of power electronics. To this end, this study investigates the feasibility of a novel integrated package assembly, which consists of copper circuit layer on an aluminum nitride (AlN) dielectric layer that is bonded to an aluminum silicon carbide (AlSiC) substrate. The entire assembly possesses a low coefficient of thermal expansion (CTE) mismatch which aids in the thermal cycling reliability of the structure. The new assembly can serve as a replacement for the conventionally used direct bonded copper (DBC)—Cu base plate—Al heat sink assembly. While improvements in thermal cycling stability of more than a factor of 18 has been demonstrated, the use of AlSiC can result in increased thermal resistance when compared to thick copper heat spreaders. To address this issue, we demonstrate that the integration of single-phase liquid cooling in the AlSiC layer can result in improved thermal performance, matching that of copper heat spreading layers. This is aided by the use of heat transfer enhancement features built into the AlSiC layer. It is found that, for a given pumping power and through analytical optimization of geometries, microchannels, pin fins, and jets can be designed to yield a heat transfer coefficients (HTCs) of up to 65,000 W m−2 K−1, which can result in competitive device temperatures as Cu-baseplate designs, but with added reliability.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(4):041002-041002-8. doi:10.1115/1.4043157.

This paper theoretically investigates the relationships among factors that affect the temperature rise of server racks and experimentally tests the influence of variable space contained arrangements on the thermal performance. To express the flow and heat transfer process of cold air in servers and analyze the critical factors affecting the temperature rise, a simplified mathematical model representing servers is developed using experimental results. An experiment is conducted within a modular data center in which cold air is supplied from a raised floor. The experiment employed a variable space of cold aisle containment and measured the resulting temperature rise, as well as pressure difference of racks and other parameters, in the simplified mathematical model. By comparing the experimental results and theoretical calculation, the theoretical model is proved to be reasonable and valid. The model predicts that the critical factors affecting the temperature rise of racks consist of static and dynamic pressure difference, total pressure of the fans, geometric structure, power consumption, resistance of doors, and opening area of servers. The result shows that the factor affected by the cold aisle contained system is the static pressure, while for the dynamic pressure difference, the contained architecture has a slight positive effect. Although the average temperature rise is quite decreased in the contained system, the static pressure distribution is nonuniform. A half-contained system which reduced contained space ratio to 50% is measured to cause a 22% increase of the static pressure difference, making a more uniform temperature distribution.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(4):041003-041003-7. doi:10.1115/1.4043645.

In this work, an easy and low-temperature fabrication method of three-dimensional (3D) ceramic substrate was proposed. A 3DPC ceramic substrate was fabricated by molding alkali-activated aluminosilicate cement (AAAC) to form up a dam (cavity) on direct plated copper (DPC) ceramic substrate at low temperature. The effects of viscosity and curing temperature of cement paste on the properties of the 3DPC were investigated. The prepared 3DPC ceramic substrate achieved precise dimensions and structure, especially the manufacturing accuracy error was less than 2.5%. By optimizing process parameters, the shear strength between dam and DPC substrate reached up to 9.5 MPa. Moreover, thermal cycle and heat resistance tests confirmed that 3DPC exhibits excellent thermal reliability. All experimental results demonstrated that 3DPC ceramic substrate could satisfy with three dimension packaging and integration.

Commentary by Dr. Valentin Fuster

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