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Guest Editorial

J. Electron. Packag. 2019;141(3):030301-030301-1. doi:10.1115/1.4043484.
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The International Technical Conference on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK) is the premier international conference for exchange of state-of-the-art knowledge in research, development, manufacturing, and applications of electronics packaging and heterogeneous integration. Founded in 1992, InterPACK is the flagship conference for the American Society of Mechanical Engineers (ASME) Electronic and Photonic Packaging Division (EPPD). The InterPACK 2018 conference was held in San Francisco, CA, Aug. 27–30.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2019;141(3):031001-031001-6. doi:10.1115/1.4042981.

White light-emitting diodes (WLEDs) composed of blue LED chip, yellow phosphor, and red quantum dots (QDs) are considered as a potential alternative for next-generation artificial light source with their high luminous efficiency (LE) and color-rendering index (CRI) while QDs' poor temperature stability and the incompatibility of QDs/silicone severely hinder the wide utilization of QDs-WLEDs. To relieve this, here we proposed a separated QDs@silica nanoparticles (QSNs)/phosphor structure, which composed of a QSNs-on-chip layer with a yellow phosphor layer above. A silica shell was coated onto the QDs surface to solve the compatibility problem between QDs and silicone. With CRI > 92 and R9 > 90, the newly proposed QSNs-based WLEDs present 16.7% higher LE and lower QDs working temperature over conventional mixed type WLEDs. The reduction of QDs' temperature can reach 11.5 °C, 21.3 °C, and 30.3 °C at driving current of 80 mA, 200 mA, and 300 mA, respectively.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031002-031002-13. doi:10.1115/1.4042984.

Thermal interface materials (TIMs) are crucial elements for packaging of power electronics. In particular, development of high-temperature lead-free die-attach TIMs for silicon carbide wide bandgap power electronics is a challenge. Among major options, sintered silver shows advantages in ease of applications. Cost, performance, reliability, and integration are concerns for technology implementation. The current study first discusses issues and status reported in literatures. Then it focuses on cost reduction and performance improvement of sintered silver using enhancement structures at micro- and nano-scales. A few design architectures are analyzed by finite element methods. The feasibility of strengthening edges and corners is also assessed. The downside of potential increase of unfavorable stresses to accelerate void coalescence would be optimized in conjunction with design concept of power electronics package modules for paths of solutions in the form of integrated systems. Demands of developing new high-temperature packaging materials to enable optimized package designs are also highlighted.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031003-031003-10. doi:10.1115/1.4043481.

Contamination due to the use of airside economizer has become a major issue that cost companies revenue. This issue will continue to rise as server components become smaller, densely packed, and as companies move into more polluted environments. Contaminants with small particles less than 10 μm are not noticeable; yet, these particles are most likely to get to areas where they can cause damage. Dust from different sources and suspended in air settles on surfaces of electrical components. The dust mainly contains two components: salts and metallic particles. The salts may be neutral or corrosive and the nature of the salt depends on the deliquescent humidity. For metallic particles, surveys are performed in various data centers in order to determine the limits in terms of weight per unit area and particle size distribution. It is necessary to first identify those contaminants that directly affect the information technology (IT) equipment in the data center. In this research, a real-world data center utilizing airside economization in an ANSI/ISA classified G2 environment was chosen for the study. Servers were removed and qualitative study of cumulative corrosion damage was carried out. The particulate contaminants were collected from different locations of a server and material characterization was performed using scanning electron microscopy (SEM), energy dispersive spectrometer (EDS), and Fourier transform infrared spectroscopy (FTIR). The analysis from these results helps to explain the impact of the contaminants on IT equipment reliability.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031004-031004-11. doi:10.1115/1.4042983.

There are various designs for segregating hot and cold air in data centers such as cold aisle containment (CAC), hot aisle containment (HAC), and chimney exhaust rack. These containment systems have different characteristics and impose various conditions on the information technology equipment (ITE). One common issue in HAC systems is a pressure build-up inside the HAC (known as backpressure). Backpressure also can be present in CAC systems in case of airflow imbalances. Hot air recirculation, limited cooling airflow rate in servers, and reversed flow through ITE with weaker fan systems (e.g., network switches) are some known consequences of backpressure. Currently, there is a lack of experimental data on the interdependency between overall performance of ITE and its internal design when backpressure is imposed on ITE. In this paper, three commercial 2-rack unit (RU) servers with different internal designs from various generations and performance levels are tested and analyzed under various environmental conditions. Smoke tests and thermal imaging are implemented to study the airflow patterns inside the tested equipment. In addition, the impact of hot air leakage into the servers through chassis perforations on the fan speed and the power consumption of the servers are studied. Furthermore, the cause of the discrepancy between measured inlet temperatures by the intelligent platform management interface (IPMI) and external sensors is investigated. It is found that arrangement of fans, segregation of space upstream and downstream of fans, leakage paths, the location of baseboard management controller (BMC) sensors, and the presence of backpressure can have a significant impact on ITE power and cooling efficiency.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031005-031005-5. doi:10.1115/1.4042982.

In this study, we realized a cylindrical tuber silicone layer for improving the light efficiency of chip-on-board light-emitting diodes (COB-LEDs) by fabricating patterned LED substrate with both silicone-wetting and silicone-repellency surfaces. To realize silicone-repellency surface, low surface energy modified nanosilica particles were prepared and deposited on the LED substrate to form porous hierarchical structure. Light efficiency enhancement for blue light COB-LEDs with pure cylindrical tuber silicone layer and white light COB-LEDs with phosphor–silicone composite layer was studied. The results show that for blue light COB-LEDs with pure cylindrical tuber silicone layer, the light efficiency increases with the contact angle and a highest light efficiency enhancement of 62.6% was achieved at 90 deg when compared to the flat silicone layer. For white light COB-LEDs at correlated color temperature (CCT) of ∼5500 K, the cylindrical tuber silicone layer enhances the light efficiency by 13.6% when compared to the conventional flat phosphor layer.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031006-031006-12. doi:10.1115/1.4043476.

Recently, microchannel heat sinks have been emerged as a kind of high performance cooling scheme to meet the heat dissipation requirement of electronics packaging and integration. In this study, an experimental investigation of subcooled flow boiling in a high-aspect-ratio rectangular microchannel was conducted with de-ionized water as the working fluid. In the experimental operations, the mass flux was varied from 200 to 400 kg/m2s and the imposed heat flux from 3 to 20 W/cm2 while the fluid inlet temperature was regulated constantly at 90 °C. The boiling curves, onset of nucleate boiling (ONB), and flow patterns of subcooled flow boiling were investigated with the aid of instrumental measurements and a high-speed camera. The slope of the boiling curves increased sharply once the superheat needed to initiate the onset of nucleate boiling was attained, with lower superheat required of boiling incipience for lower mass fluxes. Meanwhile, the initiative superheat and heat flux of onset of nucleate boiling were compared with the existing correlations in the literature with good agreement. As for the flow visualization images, slug flow and reverse backflow were observed, where transient local dryout as well as rewetting occurred. A facile image processing tool was developed to profile the transient development and progression of the liquid–vapor interface and partial dryout patches in microchannels, which proved that the physical quantities of bubble dynamics for the elongation period during subcooled boiling could be well detected and calculated.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031007-031007-7. doi:10.1115/1.4043477.
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In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN-based high-electron mobility transistor (HEMT) grown on a SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. The second approach utilizes electrical I–V characteristics of the Schottky diode neighboring to the heat source of the active transistor under different dissipated power for temperature measurement. These methods are further verified by measurements with microthermistors. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from the temperature distribution in the structure with the support of three-dimensional thermal simulation of the device. Thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The influence of individual layer properties on the thermal performance of different HEMT structures under different operating conditions is presented. The results show that the proposed experimental methods supported by simulation have a potential for the design, analysis, and thermal management of HEMT.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031008-031008-8. doi:10.1115/1.4043482.

The flow field inside the heat exchangers is associated with maximum heat transfer and minimum pressure drop. Designing a heat exchanger and employing various techniques to enhance its overall performance has been widely investigated and is still an active research. The application of elliptic tube is an effective alternative to circular tube which can reduce the pressure drop significantly. In this study, numerical simulation and optimization of variable tube ellipticity is studied. The three-dimensional numerical analysis and a multi-objective genetic algorithm (MOGA) with surrogate modeling are performed. Tubes in staggered arrangement in fin-and-tube heat exchanger are investigated for combination of various elliptic ratios and Reynolds numbers. Results show that increasing elliptic ratio increases the friction factor due to increased flow blocking area, however, the effect on the Colburn factor is not significant. Moreover, tube with lower elliptic ratio followed by higher elliptic ratio tube has better thermal-hydraulic performance. To achieve the best overall performance, the Pareto optimal strategy is adopted for which the computational fluid dynamics (CFD) results, artificial neural network (ANN), and MOGA are combined. The tubes elliptic ratio and Reynolds number are the design variables. The objective functions include Colburn factor (j) and friction factor (f). The CFD results are input into ANN model. Once the ANN is computed, it is then used to estimate the model responses as a function of inputs. The final trained ANN is used to drive the MOGA to obtain the Pareto optimal solution. The optimal values of these parameters are finally presented.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031009-031009-12. doi:10.1115/1.4043483.

The high power density of emerging electronic devices is driving the transition from remote cooling, which relies on conduction and spreading, to embedded cooling, which extracts dissipated heat on-site. Two-phase microgap coolers employ the forced flow of dielectric fluids undergoing phase change in a heated channel within or between devices. Such coolers must work reliably in all orientations for a variety of applications (e.g., vehicle-based equipment), as well as in microgravity and high-g for aerospace applications, but the lack of acceptable models and correlations for orientation- and gravity-independent operation has limited their use. Reliable criteria for achieving orientation- and gravity-independent flow boiling would enable emerging systems to exploit this thermal management technique and streamline the technology development process. As a first step toward understanding the effect of gravity in two-phase microgap flow and transport, in the present effort the authors have studied the effect of evaporator orientation, mass flux, and heat flux on flow boiling of HFE7100 in a 1.01 mm tall × 13.0 mm wide × 12.7 mm long microgap channel. Orientation-independence, defined as achieving similar critical heat fluxes (CHFs), heat transfer coefficients (HTCs), and flow regimes across orientations, was achieved for mass fluxes of 400 kg/m2 s and greater (corresponding to a Froude number of about 0.8). The present results are compared to published criteria for achieving orientation- and gravity-independence.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031010-031010-7. doi:10.1115/1.4043479.

The increasing complexity of electronics in systems used in safety critical applications, such as self-driving vehicles, requires new methods to assure the hardware reliability of the electronic assemblies. Prognostics and health management (PHM) that uses a combination of data-driven and physics-of-failure models is a promising approach to avoid unexpected failures in the field. However, to enable PHM based partly on physics-of-failure models, sensor data that measure the relevant environment loads to which the electronics are subjected during its mission life are required. In this work, the feasibility to manufacture and use integrated sensors in the inner layers of a printed circuit board (PCB) as mission load indicators measuring impacts and vibrations has been investigated. A four-layered PCB was designed in which piezoelectric sensors based on polyvinylidenefluoride-co-trifluoroethylene (PVDF-TrFE) were printed on one of the laminate layers before the lamination process. Manufacturing of the PCB was followed by the assembly of components consisting of ball grid arrays (BGAs) and quad flat no-leads (QFN) packages in a standard production reflow soldering process. Tests to ensure that the functionality of the sensor material was unaffected by the soldering process were performed. Results showed a yield of approximately 30% of the sensors after the reflow soldering process. The yield was also dependent on sensor placement and possibly shape. Optimization of the sensor design and placement is expected to bring the yield to 50% or better. The sensors responded as expected to impact tests. Delamination areas were present in the test PCBs, which requires further investigation. The delamination does not seem to be due to the presence of embedded sensors alone but rather the result of a combination of several factors. The conclusion of this work is that it is feasible to embed piezoelectric sensors in the layers of a PCB.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(3):031011-031011-11. doi:10.1115/1.4043480.

In this work, a rapid and low-cost accelerated reliability test methodology which was designed to simulate mechanical stresses induced in flip–chip bonded devices during the thermal cycling reliability test under isothermal conditions, is introduced and demonstrated using power device analogous test chips. By stressing these devices in a controlled environment, mechanical stresses become decoupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device relevant, flip–chip solder interconnects while monitoring for failure. Herein, finite element analysis (FEA) is used to extract various damage metrics of different solder materials, including PbSn37/63, SAC305, and nanosilver, in both thermal operation and the introduced alternative mechanical testing conditions. Plastic work density and strain are calculated in the critical solder interconnects as factors that indicate the amount of the damage accumulation per cycle during the mechanical cycling, thermal cycling, and power cycling tests. The number of cycles to failure for each test was calculated using the fatigue life model developed by Darveaux for eutectic PbSn solder, while for SAC305 Syed's method was used, and for nanosilver, the Knoerr et al. equations are applied. The effects of environmental temperature and shearing force frequency were studied for the mechanical cycling reliability test, where a modified Norris–Landzberg equation for mechanical cycling tests was explored using the simulation results. Finally, comparing the mechanical cycling with the equivalent thermal cycling and power cycling demonstrated a significant reduction in required test duration to achieve a reliability estimation.

Commentary by Dr. Valentin Fuster

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