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Editorial

J. Electron. Packag. 2019;141(2):020201-020201-2. doi:10.1115/1.4042738.
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The Reviewer of the Year Award is given to reviewers who have made an outstanding contribution to the journal in terms of the quantity, quality, and turnaround time of reviews completed during the past 12 months. The prize includes a Wall Plaque, 50 free downloads from the ASME Digital Collection, and a one year free subscription to the journal.

Commentary by Dr. Valentin Fuster

Review Article

J. Electron. Packag. 2019;141(2):020801-020801-17. doi:10.1115/1.4041813.

GaN-based high-power wide-bandgap semiconductor electronics and photonics have been considered as promising candidates to replace conventional devices for automotive applications due to high energy conversion efficiency, ruggedness, and superior transient performance. However, performance and reliability are detrimentally impacted by significant heat generation in the device active area. Therefore, thermal management plays a critical role in the development of GaN-based high-power electronic and photonic devices. This paper presents a comprehensive review of the thermal management strategies for GaN-based lateral power/RF transistors and light-emitting diodes (LEDs) reported by researchers in both industry and academia. The review is divided into three parts: (1) a survey of thermal metrology techniques, including infrared thermography, Raman thermometry, and thermoreflectance thermal imaging, that have been applied to study GaN electronics and photonics; (2) practical thermal management solutions for GaN power electronics; and (3) packaging techniques and cooling systems for GaN LEDs used in automotive lighting applications.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2019;141(2):021001-021001-8. doi:10.1115/1.4042668.

We provide an algorithm to optimize the geometry of the fins in an array of longitudinal-fin heat sinks (HSs) in, e.g., a blade server, which is a prohibitively long task using computational fluid dynamics (CFD). First, banks of CFD simulations are run to precompute dimensionless thermal resistances (conjugate Nusselt numbers) as a function of dimensionless HS geometry, thermophysical properties, and external parameters. These precomputed CFD results are embedded in flow network models (FNMs) in the form of look-up tables. This preserves much of the accuracy of CFD and the speed of FNM. The FNMs are, in turn, embedded in a multivariable optimization algorithm (MVO). Our hybrid numerical algorithm is provided, and we exercise it for an example problem.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(2):021002-021002-15. doi:10.1115/1.4042806.

Temperature-induced solder joint fatigue is a main reliability concern for aerospace and military industries whose electronic equipment used in the field is required to remain functional under harsh loadings. Due to the RoHS directive, which eventually will prevent lead from being utilized in electronic systems, there is a need for a better understanding of lead-free thermomechanical behavior when subjected to temperature variations. Characterizing solder joints properties remains a challenge as viscoplastic behavior during thermal cycling is complex, and their small dimensions prevent direct measurements from being performed. This paper reports the experimentation based on strain gage measurements, allowing the construction of the shear stress–strain hysteresis loop corresponding to Sn3.0Ag0.5Cu (SAC305) solder joints behavior during thermomechanical loading. This methodology, initially developed in 1984 by Hall for Sn60Pb40 interconnects, allows the measurement of the strain energy density dissipated during temperature cycles. Custom daisy-chained 76 I/O ceramic ball grid array (CBGA76) components were designed and assembled on flame retardant (FR-4) multilayered printed circuit boards (PCB). Four strain gages were specifically placed at the center of the assembly on top and bottom faces of both PCB and CBGA76 component. The assembly was subjected to temperature cycles and the SAC305 solder joints shear stress–strain hysteresis loop was plotted. The correlation between the measured strain energy density and measured lifetime corresponds to one point of the energy based fatigue curve for SAC305 solder joints. The hysteresis loop also provides the necessary data to derive SAC305 solder joints constitutive laws.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(2):021003-021003-12. doi:10.1115/1.4042471.

Potted Guidance Electronics have been widely used in precision guided munitions. In the current generation of projectiles, soft potting materials have been sufficient to protect the electronics from the G-forces of gun launch at approximately 15 kG while sustaining uncontrolled extreme low temperature storage environments at different locations around the world. With on-going development of long-range precision guided munitions, stronger and hardened potting materials will be needed to survive gun-launch accelerations of 30 kG and higher. In the case of uncontrolled storage environments, the daily temperature fluctuations can act to dislodge/fail electronic components due to the coefficient of thermal expansion (CTE) mismatches between the potting materials and the electronic components. In this paper, a new protective layer method is presented, which consists of two tightly fitted preformed polymer layers, acting to mitigate the CTE mismatches, while only producing insignificant degradation of the supporting structure during extreme high-G projectile launch. The effectiveness of this new method is demonstrated by using finite element based modeling and simulation methods to examine a simplified potted electronics example. In the first step, the example was simulated with and without protective layers during an accelerated temperature cycling (−67 °F to 185 °F), and found that the protective layers were able to mitigate the CTE mismatch problem. During second step, the example compared dynamic responses between potted electronics with and without protective layers during a high-G, ∼15 kG, gun-launch simulations; results also showed that the degradation of the supporting structure introduced by protective layers during gun launch was insignificant.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(2):021004-021004-11. doi:10.1115/1.4042472.

Foldable smartphones are expected to be widely commercialized in the near future. Thermal ground plane (TGP), known as vapor chamber or two-dimensional flat heat pipe, is a promising solution for the thermal management of foldable smartphones. There are two approaches to designing a TGP for foldable smartphones. One approach uses two TGPs connected by a graphite bridge and the other approach uses a single, large, and foldable TGP. In this study, different thermal management solutions are simulated for a representative foldable smartphone with screen dimensions of 144 × 138.3 mm2 (twice the screen of iPhone 6 s with a 10 mm gap). In addition, the simulation includes two heat sources representing a main processor with dimensions of 14.45 × 14.41 mm2 and power of 3.3 W (A9 processor in iPhone 6S) and a broadband processor with dimensions of 8.26 × 9.02 mm2 and power of 2.5 W (Qualcomm broadband processor). For the simulation, a finite element method (FEM) model is calibrated and verified by steady-state experiments of two different TGPs. The calibrated model is then used to study three different cases: a graphite heat spreader, two TGPs with a graphite hinge, and a single, large, and foldable TGP. In the fully unfolded configuration, using a graphite heat spreader, the temperature difference across the spreader's surface is about 17 °C. For the design using two TGPs connected by a graphite bridge, the temperature difference is about 7.2 °C. Finally, for the design using a single large TGP with a joint region, the temperature difference is only 1–2 °C. These results suggest that a single foldable TGP or a configuration with two TGPs outperform the graphite sheet solution for the thermal management of foldable smartphones.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(2):021005-021005-7. doi:10.1115/1.4042804.

Power electronic components' reliability depends, to a great extent, on the quality of die-attach technology. The voids appearance in the die-attach regions is almost unavoidable during the manufacturing process. The aim of this paper is to demonstrate that image processing tools enable fast and accurate void segmentation, while reducing manual interaction for X-ray monitoring of imperfect power transistor die soldering. The most common void parameters such as void area, void distribution, and shape roundness were extracted and used for statistical analysis.

Commentary by Dr. Valentin Fuster

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