Guest Editorial

J. Electron. Packag. 2019;141(1):010301-010301-1. doi:10.1115/1.4042803.

The industry of microelectronic packaging is experiencing rapid developments to meet increasing performance and function needs of modern microprocessors, mobile devices and new electronic devices for different product segments including mobile devices, PC, data centers, and other new markets. In facing of the new data era, the semiconductor industry has launched new technologies, including heterogeneous packaging integration, chiplet design and so on. It's a good time to invite the experts from the industry to share their learning and insights in the areas of electronic packaging and component integration. For this special section, a few review papers from Intel Corporation will cover broad topics of electronic packaging and thermal-mechanical challenges of server CPU for the data centers.

Commentary by Dr. Valentin Fuster

Special Section Articles

J. Electron. Packag. 2019;141(1):010801-010801-8. doi:10.1115/1.4042800.

For more than a decade, land grid array (LGA) has been one of the main central processor unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis (FEA) was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):010802-010802-10. doi:10.1115/1.4042802.

The continued demand for increasing compute performance results in an increasing system power and power density of many computers. The increased power requires more efficient cooling solutions than traditionally used air cooling. Therefore, liquid cooling, which has traditionally been used for large data center deployments, is becoming more mainstream. Liquid cooling can be used selectively to cool the high power components or the whole compute system. In this paper, the example of a fully liquid cooled server is used to describe different ingredients needed, together with the design challenges associated with them. The liquid cooling ingredients are cooling distribution unit (CDU), fluid, manifold, quick disconnects (QDs), and cold plates. Intel is driving an initiative to accelerate liquid cooling implementation and deployment by enabling the ingredients above. The functionality of these ingredients is discussed in this paper, while cold plates are discussed in detail.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):010803-010803-8. doi:10.1115/1.4042801.

The demands for both thinner bare-die ball grid array (BGA) packages and thinner thermal solutions have added complexity for the thermal enabling design and material options associated with system on chip packages in mobile personal computer (PC) platforms. The thermomechanical interactions between the bare-die package and the thermal solution are very critical, creating the needs for: (1) an in-depth thermomechanical characterization to understand their impacts on product quality and performance and (2) a simple and yet robust modeling methodology to analyze design parameters using a commercially available software. In this paper, experimental metrologies and modeling methodology are developed with the details of contents documented. Validation of the newly developed tools and recommendation/guidance are also discussed for detailed assessments of thermomechanical tradeoffs for optimal design spaces for next-generation mobile platforms.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):010804-010804-10. doi:10.1115/1.4042805.

Thermal interface materials (TIMs) play a vital role in the performance of electronic packages by enabling improved heat dissipation. These materials typically have high thermal conductivity and are designed to offer a lower thermal resistance path for efficient heat transfer. For some semiconductor components, thermal solutions are attached directly to the bare silicon die using TIM materials, while other components use an integrated heat spreader (IHS) attached on top of the die(s) and the thermal solution attached on top of the IHS. For cases with an IHS, two TIM materials are used—TIM1 is applied between the silicon die and IHS and TIM2 is used between IHS and thermal solution. TIM materials are usually comprised of a polymer matrix with thermally conductive fillers such as silica, aluminum, alumina, boron nitride, zinc oxide, etc. The polymer matrix wets the contact surface to lower the contact resistance, while the fillers help reduce the bulk resistance by increasing the bulk thermal conductivity. TIM thickness varies by application but is typically between 25 μm and around 250 μm. Selection of appropriate TIM1 and TIM2 materials is necessary for the reliable thermal performance of a product over its life and end-use conditions. It has been observed that during reliability testing, TIM materials are prone to degradation which in turn leads to a reduction in the thermal performance of the product. Typical material degradation is in the form of hardening, compression set, interfacial delamination, voiding, or excessive bleed-out. Therefore, in order to identify viable TIM materials, characterization of the thermomechanical behavior of these materials becomes important. However, developing effective metrologies for TIM characterization is difficult for two reasons: TIM materials are very soft, and the sample thickness is very small. Therefore, a well-designed test setup and a repeatable sample preparation and test procedure are needed to overcome these challenges and to obtain reliable data. In this paper, we will share some of the TIM characterization techniques developed for TIM material down-selection. The focus will be on mechanical characterization of TIM materials—including modulus, compression set, coefficient of thermal expansion (CTE), adhesion strength, and pump-out/bleed-out measurement techniques. Also, results from several TIM formulations, such as polymer TIMs and thermal gap pads, will be shared.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2019;141(1):011001-011001-7. doi:10.1115/1.4041665.

Gallium-based liquid metal (LM) inherits excellent thermophysical properties and pollution-free characteristics. However, it has long been a fatal problem that LM would cause serious corrosion and embrittlement on the classical substrate made of aluminum alloys in constructing chip cooling device. Here, anodic oxidation treatment was introduced on processing the aluminum alloy aiming to tackle the corrosion issues. The prepared anodic oxidation aluminum (AAO) coatings were composed of nanopore layers and barrier layers on a high-purity alumina matrix that were manufactured electrochemically. According to the measurement, the effective thermal conductivity of the anodized aluminum alloy increases with the total thickness of sample increasing. When the total thickness L exceeds 5 × 10−3 m, effects of the porous media on effective thermal conductivity are negligible via model simulation and calculation. It was experimentally found that aluminum alloy after surface anodization treatment presented excellent corrosion resistance and outstanding heat transfer performance even when exposed in eutectic gallium–indium (E-GaIn) LM over 200 °C. The convective heat transfer coefficient of LM for anodized sample reached the peak when the heat load is 33.3 W.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):011002-011002-9. doi:10.1115/1.4041666.

The high current densities in today's microelectronic devices and microchips lead to hotspot formations and other adverse effects on their performance. Therefore, a computational tool is needed to not only analyze but also accurately predict spatial and temporal temperature distribution while minimizing the computational effort within the chip architecture. In this study, a proper orthogonal decomposition (POD)-Galerkin projection-based reduced order model (ROM) was developed for modeling transient heat transfer in three-dimensional (3D) microchip interconnects. comsol software was used for producing the required data for ROM and for verifying the results. The developed technique has the ability to provide accurate results for various boundary conditions on the chip and interconnects domain and is capable of providing accurate results for nonlinear conditions, where thermal conductivity is temperature dependent. It is demonstrated in this work that a limited number of observations are sufficient for mapping out the entire evolution of temperature field within the domain for transient boundary. Furthermore, the accuracy of the results obtained from the developed ROM and the stability of accuracy over time is investigated. Finally, it is shown that the developed technique provides a 60-fold reduction in simulation time compared to finite element techniques.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):011003-011003-10. doi:10.1115/1.4041714.

A chip with 40 nm technology node and beyond generally incorporates low-k/ultra-low-k (LK/ULK) dielectric materials and copper traces in the back end of line (BEOL) to improve its electrical performance. Owing to the fragile low-k/ultra-low-k materials, the BEOL becomes vulnerable to external loads. When a copper pillar bump (CPB) above the BEOL sustains a shear force due to thermal mismatch between the components, failures occur in the microstructures of BEOL, especially in low-k materials. We fabricated CPBs on the chips and investigated fractures in the BEOL by a shear test approach. The shear speed and shear height are varied to examine their effects. The tested samples were analyzed via focused ion beam (FIB) and scanning electron microscope (SEM) to reveal the microstructures degradation or breaks in the BEOL, and they are classified into three kinds of failure modes. Assisted by a finite element analysis (FEA), the failure mechanism was explained and associated with the failure modes. The studies showed that the shear speed has a little influence on the maximum shear stress, but the increase of shear height leads to more fractures in the low-k materials. It indicated that decreasing the height of CPBs is helpful for reducing destruction risk of the BEOL under the thermomechanical loads. Based on a parametric study for shearing test simulation of a single CPB, the modulus and thickness of polyimide (PI) were found a larger impact on the stresses in the low-k material layer, but the modulus of low-k materials has a smaller effect on the stress. Generally, the shear test of a CPB can help to evaluate the integrity of BEOL in a chip.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):011004-011004-10. doi:10.1115/1.4041984.

Long bonding wires may swing significantly and touch with adjacent ones, which will result in short circuit under mechanical condition, especially in aerospace applications. This may seriously affect the operational reliability of high-density hermetic package components. The aim of this paper is to assess the touch risk of high-density package component under mechanical shock condition. An experiment setup, which can obtain the touch critical load and detect the wires swing touch through voltage signal captured by oscilloscope, is designed and built. To obtain the vibration data of different bonding wire structures under different shock loads, numerical simulation models are established after verified by the experimental data. Additionally, initial swing amplitude model, vibration frequency model, and damped coefficient model are established based on the simulation and experiment data. Furthermore, wire swing touch risk assessment model is established in consideration of the distribution of wire structure and shock load deviation. Based on the verified numerical simulation model, vibration characteristic parameters, including the initial swing amplitude, vibration frequency, and damped coefficient, can be calculated by numerical simulation and experimental results. The proposed method can be used to assess bonding wire touch risk in high-density hermetic package quantitatively. Potential touch risk, which cannot be reflected by failure analysis of structure damage after test, can also be detected by the electronic measurement designed in this paper. The proposed method can effectively reflect short circuit between long bonding wires of hermetic package in large shock applications, such as transport and launch.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2019;141(1):011005-011005-7. doi:10.1115/1.4042255.

Thin vapor chambers provide a novel solution to thermal management in mobile electronics. In the pursuit of vapor chamber optimization, characterization of the wicking structure can allow for a better understanding of the limitations of the device. This paper presents two novel testing methods: one for measuring the permeability of various wicking structures and another for measuring the capillary pressure. We find that the permeability of the mesh used in the wicking structure and hybridization of wicking-structures can impact what geometries limit performance, besides impacting performance directly. Specifically, while the permeability of a mesh-pillar hybrid wick follows the weighted average of the mesh and pillar permeability, the capillary pressure is determined by the capillary pore size of just the pillars or just the mesh, whichever is larger.

Commentary by Dr. Valentin Fuster

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