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Review Article

J. Electron. Packag. 2018;140(4):040801-040801-11. doi:10.1115/1.4040828.

Due to its superior electrical and thermal characteristics, silicon carbide power modules will soon replace silicon modules to be mass-produced and implemented in all-electric and hybrid-electric vehicles (HEVs). Redesign of the power modules will be required to take full advantage of these newer devices. A particular area of interest is high-temperature power modules, as under-hood temperatures often exceed maximum silicon device temperatures. This review will examine thermal packaging options for standard Si power modules and various power modules in recent all-electric and HEVs. Then, thermal packaging options for die-attach, thermal interface materials (TIM), and liquid cooling are discussed for their feasibility in next-generation silicon carbide (SiC) power modules.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2018;140(4):041001-041001-9. doi:10.1115/1.4040552.

Flexible printed circuit boards (PCBs) make it possible for engineers to design devices that use space efficiently and can undergo changes in shape and configuration. However, they also suffer from tradeoffs due to nonideal material properties. Here, a method is presented that allows engineers to introduce regions of flexibility in otherwise rigid PCB substrates. This method employs geometric features to reduce local stiffness in the PCB, rather than reducing the global stiffness by material selection. Analytical and finite element models are presented to calculate the maximum stresses caused by deflection. An example device is produced and tested to verify the models.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(4):041002-041002-10. doi:10.1115/1.4040670.

The design of three-dimensional (3D) power delivery network (PDN) is constrained by both power and thermal integrity. Through-silicon via (TSV) as an important part of transmission power and heat in stack, the rational design of TSV layout is particularly important. Using minimal TSV area to achieve the required 3D PDN is significant to reduce manufacturing costs and increase integration. In this paper, we propose electrical and thermal models of 3D PDN, respectively, and we use them to solve the 3D voltage drop and temperature distribution problems. The accuracy and efficiency of our proposed methods are demonstrated by simulation measurement. Combining these two methods, a layer-based optimization solution is developed and allows us to adjust the TSV density for different layers while satisfying the global power and thermal constraints. This optimization is scalable and has the same guiding value for multichip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(4):041003-041003-11. doi:10.1115/1.4040924.

A novel reliability evaluation procedure of lead-free solders used in electronic packaging (EP) subjected to thermomechanical loading is proposed. A solder ball is represented by finite elements (FEs). Major sources of nonlinearities are incorporated as realistically as practicable. Uncertainties in all design variables are quantified using available information. The thermomechanical loading is represented by five design parameters and uncertainties associated with them are incorporated. Since the performance or limit state function (LSF) of such complicated problem is implicit in nature, it is approximately generated explicitly in the failure region with the help of a completely improved response surface method (RSM)-based approach and the universal Kriging method (KM). The response surface (RS) is generated by conducting as few deterministic nonlinear finite element analyses as possible by integrating several advanced factorial mathematical concepts producing compounding beneficial effect. The accuracy, efficiency, and application potential of the procedure are established with the help of Monte Carlo simulation (MCS) and the results from laboratory investigation reported in the literature. The study conclusively verified the proposed method. Similar studies can be conducted to fill the knowledge gap for cases where the available analytical and experimental studies are limited or extend the information to cases where reliability information is unavailable. The study showcased how reliability information can be extracted with the help of multiple deterministic analyses. The authors believe that they proposed an alternative to the classical MCS technique.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(4):041004-041004-9. doi:10.1115/1.4040923.

In this work, a sinusoidal vibration test method with resonance tracking is employed for reliability testing of circuit assemblies. The system continuously monitors for changes in the resonant frequency of the circuit board and adjusts the excitation frequency to match the resonant frequency. The test setup includes an electrodynamic shaker with a real-time vibration control, resistance monitoring for identifying electrical failures of interconnects, and vibration logging for monitoring changes in the dynamic response of the assembly over time. Reliability tests were performed using the resonance tracking sinusoidal test method for assemblies, each consisting of a centrally mounted ball grid array (BGA) device assembled with 63Sn37Pb and SAC105 solder alloys. These tests show that the resonance tracking method gives more consistent failure times. Failure analysis for the tested devices shows the primary failure mode is “input” trace crack first, followed by fatigue through the solder for complete failure. A finite element (FE) model, correlated with experimental modal analysis, is shown to accurately estimate the circuit board deflection estimated from the harmonic vibration data. This provides a means of estimating the stresses in the electronic interconnections while accounting for the variability between test parts. These fine-tuned vibration measurement techniques and related FE models provide the building blocks for high cycle solder fatigue plots (i.e., S–N curves).

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(4):041007-041007-10. doi:10.1115/1.4041014.

In this work, the elastic–plastic properties of the printed interconnects on a glass substrate with Ag-filled polymer-conductor ink are evaluated through a theoretical framework based on finite element (FE) modeling of instrumented sharp indentation, experimental indentation, the concept of the representative strain, and dimensional analysis. Besides, the influences of the ink-solvent content and temperature on the elastic–plastic and electrical properties of the printed Ag-based interconnects are also addressed. First of all, parametric FE indentation analyses are carried out over a wide range of elastic–plastic material parameters. These parametric results together with the concept of the representative strain are used via dimensional analysis to constitute a number of dimensionless functions, and further the forward/reverse algorithms. The forward algorithm is used for describing the indentation load–depth relationship and the reverse for predicting the elastic–plastic parameters of the printed Ag-based interconnects. The proposed algorithms are validated through the correct predictions of the plastic properties of three known metals. At last, their surface morphology, microstructure, and elemental composition are experimentally characterized. Results show that the elastic–plastic properties and electrical sheet resistance of the printed Ag-based interconnects increase with the ink-solvent content, mainly due to the increase of carbon element as a result of the increased ink-solvent residue, whereas their elastic–plastic properties and electrical performance decreases with the temperature.

Commentary by Dr. Valentin Fuster

Technical Brief

J. Electron. Packag. 2018;140(4):044501-044501-3. doi:10.1115/1.4040829.

The conjecture discussed in our previous paper [Jaeger, R. C., Motalab, M., Hussain, S., and Suhling, J. C., 2014, “Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors,” ASME J. Electron. Packag., 136(4), p. 041014; Jaeger, R. C., Motalab, M., Hussain, S., and Suhling, J. C., 2018, Erratum: “Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors,” ASME J. Electron. Packag., 140(1), p. 017001] was backed up by measurements and simulation results, but not mathematically proven. A proof based upon two-port impedance parameter reciprocity is presented with additional experimental confirmation.

Topics: Sensors , Stress
Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(4):044502-044502-5. doi:10.1115/1.4040794.

The incorporation of a micro copper pillar is considered as the major interconnection method in three-dimensional (3D) integrated circuit (IC) intergradation under high-density I/O conditions. To achieve low-temperature bonding, this study investigated the thermosonic flip chip bonding of a copper pillar with a tin cap. The effect of bonding force on bonding strength was studied, and an average bonding strength 2500 g (approximately 84.8 MPa) was obtained in 2 s, at an optimized bonding force of 0.11 N per 40 μm pillar bump, and substrate temperature of 200 °C. Additionally, the effect of the bonding force on bonding interface microstructure and intermetallic compounds (IMCs) was also investigated. Tin whiskers were also observed at the bonding interface at low bonding forces.

Commentary by Dr. Valentin Fuster

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