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Guest Editorial

J. Electron. Packag. 2018;140(1):010301-010301-1. doi:10.1115/1.4039090.
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InterPACK is a premier international forum for exchange of state-of-the-art knowledge in research, development, manufacturing, and applications of micro-electronics packaging. It is the flagship conference of the ASME Electronic and Photonic Packaging Division (EPPD) founded in 1992 as an ASME-JSME joint biannual conference.

Commentary by Dr. Valentin Fuster

Review Article

J. Electron. Packag. 2018;140(1):010801-010801-11. doi:10.1115/1.4038392.
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Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

Commentary by Dr. Valentin Fuster

SPECIAL SECTION PAPERS

J. Electron. Packag. 2018;140(1):010901-010901-11. doi:10.1115/1.4039091.

Gravity-driven two-phase liquid cooling systems using flow boiling within microscale evaporators are becoming a game-changing solution for electronics cooling. The optimization of the system's filling ratio (FR) can however become a challenging problem for a system operating over a wide range of cooling capacities and temperature ranges. The benefits of a liquid accumulator (LA) to overcome this difficulty are evaluated in the present paper. An experimental thermosyphon cooling system was built to cool multiple electronic components up to a power dissipation of 1800 W. A double-ended cylinder with a volume of 150 cm3 is evaluated as the LA for two different system volumes (associated with two different condensers). Results demonstrated that the LA provided robust thermal performance as a function of FR for the entire range of heat loads tested. In addition, the present LA was more effective for a small volume system, 599 cm3, than for a large volume system, 1169 cm3, in which the relative size of the LA increased from 12.8% to 25% of the total system's volume.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):010902-010902-10. doi:10.1115/1.4039025.

This paper presents an experimentally validated room-level computational fluid dynamics (CFD) model for raised-floor data center configurations employing active tiles. Active tiles are perforated floor tiles with integrated fans, which increase the local volume flow rate by redistributing the cold air supplied by the computer room air conditioning (CRAC) unit to the under-floor plenum. The numerical model of the data center room consists of one cold aisle with 12 racks arranged on both sides and three CRAC units sited around the periphery of the room. The commercial CFD software package futurefacilities6sigmadcx is used to develop the model for three configurations: (a) an aisle populated with ten (i.e., all) passive tiles; (b) a single active tile and nine passive tiles in the cold aisle; and (c) an aisle populated with all active tiles. The predictions from the CFD model are found to be in good agreement with the experimental data, with an average discrepancy between the measured and computed values for total flow rate and rack inlet temperature less than 4% and 1.7 °C, respectively. The validated models were then used to simulate steady-state and transient scenarios following cooling failure. This physics-based and experimentally validated room-level model can be used for temperature and flow distributions prediction and identifying optimal number and locations of active tiles for hot spot mitigation in data centers.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):010903-010903-12. doi:10.1115/1.4039333.

The revolutionary changes in automotive industry toward fully connected automated electrical vehicles necessitate developments in automotive electronics at unprecedented speed. Signal, control, and power electronics will heterogeneously be integrated at minimum space with sensors and actuators to form highly compact and ultra-smart systems for functions like traction, lighting, energy management, computation, and communication. Most of these systems will be highly safety relevant with the requirements in system availability exceeding today's already high automotive standards. Unlike the human drivers of today, passengers in the automated car do not pay constant attention to the driving actions of the vehicle. Hence, reliability research is massively challenged by the new automotive applications. Guaranteeing the specified lifetime at statistical average is no longer sufficient. Assuring that no failure of an individual safety relevant part occurs unexpectedly becomes most important. The paper surveys the priority actions underway to cope with the tremendous challenges. It highlights practical examples in all three directions of reliability research: (i) Experimental reliability tests and physical analyses: New and highly efficient accelerated stress tests are able to cover the complex and multifold loading situation in the field. New analytics techniques can identify the typical failure modes and their physical root causes; (ii) Virtual techniques: Schemes of validated simulations allow capturing the physics of failure (PoF) proactively in the design for reliability (DfR) process; and (iii) Prognostics health management (PHM). A new concept is introduced for adding a minimum of PHM features at various levels of automotive electronics to provide functional safety as required for autonomous vehicles. This way, the new generation of reliability methods will continuously provide estimates of the remaining useful life (RUL) for each relevant part under the actual use conditions to allow triggering maintenance in time

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):010904-010904-10. doi:10.1115/1.4039020.
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Rapid advancement of modern electronics has pushed the limits of traditional thermal management techniques. Novel approaches to the manipulation of the flow of heat in electronic systems have potential to open new design spaces. Here, the field of thermal metamaterials as it applies to electronics is briefly reviewed. Recent research and development of thermal metamaterial systems with anisotropic thermal conductivity for the manipulation of heat flow in ultra-thin composites is explained. An explanation of fundamental experimental studies on heat flow control using standard printed circuit board (PCB) technology follows. From this, basic building blocks for heat flux cloaking, focusing, and reversal are reviewed, and their extension to a variety of electronics applications is emphasized. While device temperature control, thermal energy harvesting, and electrothermal circuit design are the primary focus, some discussion on the extension of thermal guiding (TG) structures to device-scale applications is provided. In total, a holistic view is offered of the myriad of possible applications of thermal metamaterials to heat flow control in future electronics.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):010905-010905-8. doi:10.1115/1.4039026.

Large thermal gradients represent major operational hazards in microprocessors; hence, there is a critical need to monitor possible hot spots both accurately and in real time. Thermal monitoring in microprocessors is typically performed using temperature sensors embedded in the electronic board. The location of the temperature sensors is primarily determined by the sensor space claim rather than the ideal location for thermal management. This paper presents an optimization methodology to determine the most beneficial locations for the temperature sensors inside of the microprocessors, based on input from high-resolution surface infrared thermography combined with inverse heat transfer solvers to predict hot spot locations. Specifically, the infrared image is used to obtain the temperature map over the processor surface, and subsequently delivers the input to a three-dimensional (3D) inverse heat conduction methodology, used to determine the temperature field within the processor. In this paper, simulated thermal maps are utilized to assess the accuracy of this method. The inverse methodology is based on a function specification method combined with a sequential regularization in order to increase accuracy in the results. Together with the number of sensors, the temperature field within the processor is then used to determine the optimal location of the temperature sensors using a genetic algorithm optimization combined with a Kriging interpolation. This combination of methodologies was validated against the finite element analysis of a chip incorporating heaters and temperature sensors. An uncertainty analysis of the inverse methodology and the Kriging interpolation was performed separately to assess the reliability of the procedure.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):010906-010906-7. doi:10.1115/1.4039027.

Predominant high melting point solders for high-temperature and harsh environment electronics (operating temperatures from 200 to 250 °C) are Pb-based systems, which are being subjected to RoHS regulations because of their toxic nature. In this study, high bismuth (Bi) alloy compositions with Bi-XSb-10Cu (X from 10 wt % to 20 wt %) were designed and developed to evaluate their potential as high-temperature, Pb-free replacements. Reflow processes were developed to make die-attach samples made from the cast Bi alloys. Die-attach joints made from Bi-15Sb-10Cu alloy exhibited an average shear strength of 24 MPa, which is comparable to that of commercially available high Pb solders. These alloy compositions also retained original shear strength even after thermal shock (TS) between −55 °C and +200 °C and high-temperature storage (HTS) at 200 °C. Brittle interfacial fracture sometimes occurred along the interfacial NiSb layer formed between Bi(Sb) matrix and Ni metallized surface. In addition, heat dissipation capabilities, using flash diffusivity, were measured on the die-attach assembly and were compared to the corresponding bulk alloys. The thermal conductivity of all the Bi–Sb alloys was higher than that of pure Bi. By creating high volume fraction of precipitates in a die-attach joint microstructure, it was feasible to further increase thermal conductivity of this joint to 24 W/m·K, which is three times higher than that of pure Bi (8 W/m·K). Bi–15Sb–10Cu alloy has so far shown the most promising performance as a die-attach material for high-temperature applications (operated over 200 °C). Hence, this alloy was further studied to evaluate its potential for plastic deformation. Bi–15Sb–10Cu alloy has shown limited plastic deformation in room temperature tensile testing in which premature fracture occurred via the cracks propagated on the (111) cleavage planes of rhombohedral crystal structure of the Bi(Sb) matrix. The same alloy has, however, shown up to 7% plastic strain under tension when tested at 175 °C. The cleavage planes, which became oriented at smaller angles to the tensile stress, contributed to improved plasticity in the high-temperature test.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):010907-010907-12. doi:10.1115/1.4039028.

In raised floor data centers, tiles with high open area ratio or complex understructure are used to fulfill the demand of today's high-density computing. Using more open tiles reduces the pressure drop across the raised floor with the potential advantages of increased airflow and lower noise. However, it introduces the disadvantage of increased nonuniformity of airflow distribution. In addition, there are various tile designs available on the market with different opening shapes or understructures. Furthermore, a physical separation of cold and hot aisles (containment) has been introduced to minimize the mixing of cold and hot air. In this study, three types of floor tiles with different open area, opening geometry, and understructure are considered. Experimentally validated detail models of tiles were implemented in computational fluid dynamics (CFD) simulations to address the impact of tile design on the cooling of information technology (IT) equipment in both open and enclosed aisle configurations. Also, impacts of under-cabinet leakage on the IT equipment inlet temperature in the provisioned and under-provisioned scenarios are studied. In addition, a predictive equation for the critical under-provisioning point that can lead to a no-flow condition in IT equipment with weaker airflow systems is presented. Finally, the impact of tile design on thermal performance in a partially enclosed aisle with entrance doors is studied and discussed.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2018;140(1):011001-011001-6. doi:10.1115/1.4038391.

The notion of permeability is very important in understanding and modeling the flow behavior of fluids in a special type of porous medium (i.e., the underfill flow in flip-chip packaging). This paper presents a new concept regarding permeability in a porous medium, namely two types of permeability: superficial permeability (with consideration of both the pore cross-sectional area and the solid matrix cross-sectional area) and pore permeability (with consideration of the pore cross-sectional area only). Subsequently, the paper proposes an analytical model (i.e., equation) for the pore permeability and superficial permeability of an underfill porous medium in a flip-chip packaging, respectively. The proposed model along with several similar models in literature is compared with a reliable numerical model developed with the computational fluid dynamics (CFD) technique, and the result of the comparison shows that the proposed model for permeability is the most accurate one among all the analytical models in literature. The main contributions of the paper are as follows: (1) the provision of a more accurate analytical model for the permeability of an underfill porous medium in flip-chip packaging, (2) the finding of two types of permeability depending on how the cross-sectional area is taken, and (3) the correction of an error in the others' model in literature.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):011002-011002-9. doi:10.1115/1.4038245.

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(1):011003-011003-11. doi:10.1115/1.4038861.

The ripening growth kinetics of interfacial Cu6Sn5 grains between Cu substrates and Sn-3.0Ag-0.5Cu-xTiO2 (x = 0, 0.02, 0.05, 0.1, 0.3, and 0.6 wt %) (SAC305-xTiO2) solders were investigated. The results show that the Cu6Sn5 grain morphology is affected by the solder composition and the reflow time. The Cu6Sn5 grain size decreases upon addition of TiO2 and shows a significant decrease when the TiO2 nanoparticle fraction is increased to 0.1 wt %. At higher TiO2 nanoparticle fractions, the Cu6Sn5 grain size increases slightly. The growth of the Cu6Sn5 grains is mainly supplied by the flux of the interfacial reaction and the flux of ripening; the ripening flux plays a dominant role because it is approximately one order of magnitude greater than the interfacial reaction flux. The ripening growth of the Cu6Sn5 grains in the TiO2-containing solder joints is reduced more effectively than that of the Cu6Sn5 grains in the TiO2-free joint. For the SAC305/Cu and SAC305-0.6TiO2/Cu solder joints, the particle size distribution (PSD) of the Cu6Sn5 grains is well fit with the Marqusee and Ross (MR) model when the normalized size value of r/<r> is less than 1, and it is consistent with the flux-driven ripening (FDR) model when the value of r/<r> is greater than 1. On the other hand, for the SAC305-0.1TiO2/Cu solder joint, the Cu6Sn5 grains with a nearly hemispheric scallop shape and the PSD of the Cu6Sn5 grains show good agreement with the FDR model.

Commentary by Dr. Valentin Fuster

Errata

J. Electron. Packag. 2018;140(1):017001-017001-1. doi:10.1115/1.4038735.

Fig. 1

Analysis by superposition: (a) diagonal current excitation; (b) and (c) equivalent circuits for superposition

Grahic Jump LocationAnalysis by superposition: (a) diagonal current excitation; (b) and (c) equivalent circuits for superposition

Commentary by Dr. Valentin Fuster

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