Guest Editorial

J. Electron. Packag. 2017;139(2):020301-020301-1. doi:10.1115/1.4036627.

ASME's International Mechanical Engineering Congress and Exposition (IMECE), held from Nov. 11 to 17, 2016, at the Phoenix Convention Center, Phoenix, AZ, is the largest interdisciplinary mechanical engineering conference in the world. IMECE plays a significant role in stimulating innovation from basic discovery to translational application. It fosters new collaborations that engage stakeholders and partners not only from academia but also from national laboratories, industries, research settings, and funding bodies. In 2016, the ASME Electronic and Photonic Packaging Division (EPPD) co-organized the technical track on Micro- and Nano-Systems Engineering and Packaging. Authors and presenters were invited to participate in this event to expand international cooperation, understanding, and promotion of efforts in the area of electronics and photonics packaging. Technical publications were presented in a broad range of relevant areas, including: (1) quality and reliability of electronics and photonics packaging; (2) manufacturing processes, materials, and flexible technologies; (3) advanced 2.5D/3D packaging; (4) thermoelectric devices; (5) thermal modeling techniques; and (6) electronics and photonics thermal management, with special invited talks on the topics of electrocaloric cooling and high-bandwidth packaging challenges. Based on the conference peer-reviews, the authors of few select papers were invited to submit a paper for this Special Section issue. These papers were then subject to the independent peer-review process in accordance with the editorial procedures of the ASME Journal of Electronic Packaging (JEP).

Commentary by Dr. Valentin Fuster


J. Electron. Packag. 2017;139(2):020901-020901-7. doi:10.1115/1.4036065.

For thermal management architectures wherein the heat sink is embedded close to a dynamic heat source, nonuniformities may propagate through the heat sink base to the coolant. Available transient models predict the effective heat spreading resistance to calculate chip temperature rise, or simplify to a representative axisymmetric geometry. The coolant-side temperature response is seldom considered, despite the potential influence on flow distribution and stability in two-phase microchannel heat sinks. This study solves three-dimensional transient heat conduction in a Cartesian chip-on-substrate geometry to predict spatial and temporal variations of temperature on the coolant side. The solution for the unit step response of the three-dimensional system is extended to any arbitrary temporal heat input using Duhamel's method. For time-periodic heat inputs, the steady-periodic solution is calculated using the method of complex temperature. As an example case, the solution of the coolant-side temperature response in the presence of different transient heat inputs from multiple heat sources is demonstrated. To represent a case where the thermal spreading from a heat source is localized, the problem is simplified to a single heat source at the center of the domain. Metrics are developed to quantify the degree of spatial and temporal nonuniformity in the coolant-side temperature profiles. These nonuniformities are mapped as a function of nondimensional geometric parameters and boundary conditions. Several case studies are presented to demonstrate the utility of such maps.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020902-020902-11. doi:10.1115/1.4036356.

This paper describes the use of the double cantilever beam (DCB) method for characterizing the adhesion strength of interfaces in advanced microelectronic packages at room and high temperatures. Those interfaces include silicon–epoxy underfill, solder resist–epoxy underfill and epoxy mold compounds (EMCs), and die passivation materials–epoxy underfill materials. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon–underfill samples and cracking of solder resist films in solder resist–underfill samples. An asymmetric DCB configuration (i.e., different cantilever beam thickness on top compared to the bottom) was found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Furthermore, in order to characterize the adhesion strength of those interfaces at elevated temperatures seen during package assembly and end-user testing, an environmental chamber was designed and fabricated to rapidly and uniformly heat the DCB samples for testing at high temperatures. This chamber was used to successfully measure the adhesion strength of silicon–epoxy underfill samples at temperatures up to 260 °C, which is the typical maximum temperature experienced by electronic packages during solder reflow. For the epoxy underfills tested in this study, the DCB samples failed cohesively within the underfill at room temperature but started failing adhesively at temperatures near 150 °C. Adhesion strength measurements also showed a clear degradation with temperature. Several other case studies using DCB for material selection and assembly process optimization are also discussed. Finally, fractography results of the fractured surfaces are presented for better understanding of the failure mode.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020903-020903-11. doi:10.1115/1.4036363.

Deployment of airside economizers (ASEs) in data centers is rapidly gaining acceptance to reduce cost of cooling energy by reducing hours of operation of computer room air conditioning (CRAC) units. Airside economization has associated risk of introducing gaseous and particulate contamination into data centers, thus degrading the reliability of information technology (IT) equipment. The challenge is to determine reliability degradation of IT equipment if operated in environmental conditions outside American Society of Heating, Refrigeration, and Air-Conditioning Engineers (ASHRAE) recommended envelope with contamination severity levels higher than G1. This paper is a first attempt at addressing this challenge by studying the cumulative corrosion damage to IT equipment operated in an experimental modular data center (MDC) located in an industrial area with measured level of air contaminants in ISA severity level G2. This study serves several purposes including: correlating IT equipment reliability to levels of airborne corrosive contaminants and studying degree of reliability degradation when IT equipment is operated outside ASHRAE recommended envelope at a location with high levels of contaminants. Reliability degradation of servers exposed to outside air via an airside economizer was determined qualitatively by examining corrosion of components in these servers and comparing the results to corrosion of components in other similar servers that were stored in a space where airside economization was not used. In the 4 years of the modular data center's servers' operation, none of the servers failed. This observation highlights an opportunity to significantly save data center cooling energy by allowing IT equipment to operate outside the currently recommended and allowable ASHRAE envelopes and outside the ISA severity level G1.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020904-020904-7. doi:10.1115/1.4036384.

Engineered porous structures are being used in many applications including aerospace, electronics, biomedical, and others. The objective of this paper is to study the effect of three-dimensional (3D)-printed porous microstructure on the dielectric characteristics for radio frequency (RF) antenna applications. In this study, a sandwich construction made of a porous acrylonitrile butadiene styrene (ABS) thermoplastic core between two solid face sheets has been investigated. The porosity of the core structure has been varied by changing the fill densities or percent solid volume fractions in the 3D printer. Three separate sets of samples with dimensions of 50 mm × 50 mm × 5 mm are created at three different machine preset fill densities each using LulzBot and Stratasys dimension 3D printers. The printed samples are examined using a 3D X-ray microscope to understand pore distribution within the core region and uniformity of solid volumes. The nondestructively acquired 3D microscopy images are then postprocessed to measure actual solid volume fractions within the samples. This measurement is important specifically for dimension-printed samples as the printer cannot be set for any specific fill density. The experimentally measured solid volume fractions are found to be different from the factory preset values for samples prepared using LulzBot printer. It is also observed that the resonant frequency for samples created using both the printers decreases with an increase in solid volume fraction, which is intuitively correct. The results clearly demonstrate the ability to control the dielectric properties of 3D-printed structures based on prescribed fill density.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020905-020905-7. doi:10.1115/1.4036389.

Stretchable electronics have been a subject of increased research over the past decade (Lacour, S., et al., 2006, “Mechanisms of Reversible Stretchability of Thin Metal Films on Elastomeric Substrates,” Appl. Phys. Lett., 88(20), p. 204103; Lacour, S., et al., 2004, “Design and Performance of Thin Metal Film Interconnects for Skin-Like Electronic Circuits,” IEEE Electron Device Lett., 25(4), pp. 179–181; and Maghribi, M., et al., 2005, “Stretchable Micro-Electrode Array,” International IEEE-EMBS Conference on Microtechnologies in Medicine and Biology, pp. 80–83.). Although stretchable electronic devices are a relatively new area for the semiconductor/electronics industries, recent market research indicates that the market could be worth more than $900 million by 2023 (PR Newswire, 2015, “Stretchable Electronics Market Worth $911.37 Million by 2023,” PR Newswire, Albuquerque, NM.). This paper investigates mechanical testing methods designed to test the stretching capabilities of potential products across the electronics industry to help quantify and understand the mechanical integrity, response, and the reliability of these devices. Typically, the devices consist of stiff modules connected by stretchable traces (Loher, T., et al., 2006, “Stretchable Electronic Systems,” Electronics Packaging Technology Conference (EPTC '06), pp. 271–276.). They require electrical and mechanical connectivity between the modules to function. In some cases, these devices will be subject to biaxial and/or cyclic mechanical strain, especially for wearable applications. The ability to replicate these mechanical strains and understand their effect on the function of the devices is critical to meet performance, process, and reliability requirements. In this paper, methods for simulating biaxial and out-of-plane strains similar to what may occur in a wearable device on the human body are proposed. Electrical and/or optical monitoring (among other methods) can be used to determine cycles to failure depending on expected failure modes. Failure modes can include trace damage in stretchable regions, trace damage in functional component regions, or bulk stretchable material damage, among others. Three different methods of applying mechanical strain are described, including a stretchable air bladder method, membrane test method, and lateral expansion method.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020906-020906-12. doi:10.1115/1.4036402.

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020907-020907-8. doi:10.1115/1.4036403.

In recent years, light emitting diodes (LEDs) have become an attractive technology for general and automotive illumination systems replacing old-fashioned incandescent and halogen systems. LEDs are preferable for automobile lighting applications due to its numerous advantages such as low power consumption and precise optical control. Although these solid state lighting (SSL) products offer unique advantages, thermal management is one of the main issues due to severe ambient conditions and compact volume. Conventionally, tightly packaged double-sided FR4-based printed circuit boards (PCBs) are utilized for both driver electronic components and LEDs. In fact, this approach will be a leading trend for advanced internet of things applications embedded LED systems in the near future. Therefore, automotive lighting systems are already facing with tight-packaging issues. To evaluate thermal issues, a hybrid study of experimental and computational models is developed to determine the local temperature distribution on both sides of a three-purpose automotive light engine for three different PCB approaches having different materials but the same geometry. Both results showed that FR4 PCB has a temperature gradient (TMaxBoard to TAmbient) of over 63 °C. Moreover, a number of local hotspots occurred over FR4 PCB due to low thermal conductivity. Later, a metal core PCB is investigated to abate local hot spots. A further study has been performed with an advanced heat spreader board based on vapor chamber technology. Results showed that a thermal enhancement of 7.4% and 25.8% over Al metal core and FR4-based boards with the advanced vapor chamber substrate is observed. In addition to superior thermal performance, a significant amount of lumen extraction in excess of 15% is measured, and a higher reliability rate is expected.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020908-020908-6. doi:10.1115/1.4036404.

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020909-020909-7. doi:10.1115/1.4036405.

In this paper, heat transfer enhancement using liquid–liquid Taylor flow in miniscale curved tubing for isothermal boundary conditions is examined. Copper tubing with an inner tube diameter of D = 1.65 mm and different radii of curvature and lengths is used in the experiments. Taylor flow is created using water and low-viscosity silicone oils (0.65 cS, 1 cS, and 3 cS) to examine the effect of Prandtl number on heat transfer rates in curved tubing. A series of experiments are conducted using tubing with constant length and variable curvature as well as variable length and constant curvature. The experimental results are compared with models for liquid–liquid Taylor flow in straight tubing and single-phase flow in curved tubes. The results of the research highlight the effects of liquid–liquid Taylor flow in curved tubing. This research provides new insights into the effect of curvature on heat transfer enhancement for liquid–liquid Taylor flow in miniscale curved tubing, at a constant wall temperature.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020910-020910-10. doi:10.1115/1.4036406.

Due to the compact and modular nature of CubeSats, thermal management has become a major bottleneck in system design and performance. In this study, we outline the development, initial testing, and modeling of a flat, conformable, lightweight, and efficient two-phase heat strap called FlexCool, currently being developed at Roccor. Using acetone as the working fluid, the heat strap has an average effective thermal conductivity of 2149 W/m K, which is approximately five times greater than the thermal conductivity of pure copper. Moreover, the heat strap has a total thickness of only 0.86 mm and is able to withstand internal vapor pressures as high as 930 kPa, demonstrating the suitability of the heat strap for orbital environments where pressure differences can be large. A reduced-order, closed-form theoretical model has been developed in order to predict the maximum heat load achieved by the heat strap for different design and operating parameters. The model is validated using experimental measurements and is used here in combination with a genetic algorithm to optimize the design of the heat strap with respect to maximizing heat transport capability.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020911-020911-7. doi:10.1115/1.4036442.

Dominant factors of electromigration (EM) resistance of electroplated copper thin-film interconnections were investigated from the viewpoint of temperature and crystallinity of the interconnection. The EM test under the constant current density of 7 mA/cm2 was performed to observe the degradation such as accumulation of copper atoms and voids. Formation of voids and the accumulation occurred along grain boundaries during the EM test, and finally the interconnection was fractured at the not cathode side but at the center part of the interconnection. From the monitoring of temperature of the interconnection by using thermography during the EM test, this abnormal fracture was caused by large Joule heating of itself under high current density. In order to investigate the effect of grain boundaries on the degradation by EM, the crystallinity of grain boundaries in the interconnection was evaluated by using image quality (IQ) value obtained from electron backscatter diffraction (EBSD) analysis. The crystallinity of grain boundaries before the EM test had wide distribution, and the grain boundaries damaged under the EM loading mainly were random grain boundaries with low crystallinity. Thus, high density of Joule heating and high-speed diffusion of copper atoms along low crystallinity grain boundaries accelerated the EM degradation of the interconnection. The change of Joule heating density and activation energy for the EM damage were evaluated by using the interconnection annealed at 400 °C for 3 h. The annealing of the interconnection increased not only average grain size but also crystallinity of grains and grain boundaries drastically. The average IQ value of the interconnection was increased from 4100 to 6200 by the annealing. The improvement of the crystallinity decreased the maximum temperature of the interconnection during the EM test and increased the activation energy from 0.72 eV to 1.07 eV. The estimated lifetime of interconnections is increased about 100 times by these changes. Since the atomic diffusion is accelerated by not only the current density but also temperature and low crystallinity grain boundaries, the lifetime of the interconnections under EM loading is a strong function of their crystallinity. Therefore, it is necessary to evaluate and control the crystallinity of interconnections quantitatively using IQ value to assure their long-term reliability.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):020912-020912-7. doi:10.1115/1.4036661.

As semiconductor packaging technologies continue to scale, it drives the use of existing and new materials in thin layer form factors. Increasing packaging complexity implies that materials in thin layers are subject to nontrivial loading conditions, which may exceed the toughness of the material, leading to cracks. It is important to ensure that the reliability of these low-cost materials is at par or better than currently used materials. This in turn leads to significant efforts in the area of material characterization at the lab level to speed up the development process. Methods for testing and characterizing fracture-induced failures in various material systems in electronic packaging are investigated in this paper. The learnings from different test methods are compared and discussed here. More specifically, different fracture characterization techniques on (a) freestanding “thin” solder-resist films and (b) filled “bulk” epoxy materials such as underfills and epoxy mold compounds are investigated. For thin films, learnings from different test methods for measuring fracture toughness, namely, uniaxial tension (with and without an edge precrack) and membrane penetration tests, are discussed. Reasonably good agreement is found between the various thin film toughness test methods; however, ease of sample preparation, fixture, and adaptability to environmental testing will be discussed. In the case of filled epoxy resin systems, the single-edge-notched bending (SENB) technique is utilized to obtain the fracture toughness of underfills and mold compounds with filler materials. Learnings on different methods of creating precracks in SENB samples are also investigated and presented.

Commentary by Dr. Valentin Fuster

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