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IN THIS ISSUE

Review Article

J. Electron. Packag. 2016;138(4):040801-040801-12. doi:10.1115/1.4034317.
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In the first part of this paper, a review of fundamental experimental studies on flow boiling in plain and surface enhanced microgaps is presented. In the second part, complimentary to the literature review, new results of subcooled flow boiling of water through a micropin-fin array heat sink with outlet pressure below atmospheric are presented. A 200 μm high microgap device design was tested, with a longitudinal pin pitch of 225 $μm$, a transverse pitch of 135 $μm$, and a diameter of 90 $μm$, respectively. Tested mass fluxes ranged from 1351 to 1784 , and effective heat flux ranged from 198 to 444 W/cm2 based on the footprint surface area. The inlet temperature varied from 6 to 12 °C, and outlet pressure ranged from 24 to 36 kPa. The two-phase heat transfer coefficient showed a decreasing trend with increasing heat flux. High-speed visualizations of flow patterns revealed a triangular wake after bubble nucleation. Flow oscillations were seen and discussed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):040802-040802-19. doi:10.1115/1.4034605.
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Thermal conductivity and interfacial thermal conductance play crucial roles in the design of engineering systems where temperature and thermal stress are of concerns. To date, a variety of measurement techniques are available for both bulk and thin film solid-state materials with a broad temperature range. For thermal characterization of bulk material, the steady-state method, transient hot-wire method, laser flash diffusivity method, and transient plane source (TPS) method are most used. For thin film measurement, the 3ω method and the transient thermoreflectance technique including both time-domain and frequency-domain analysis are widely employed. This work reviews several most commonly used measurement techniques. In general, it is a very challenging task to determine thermal conductivity and interfacial thermal conductance with less than 5% error. Selecting a specific measurement technique to characterize thermal properties needs to be based on: (1) knowledge on the sample whose thermophysical properties are to be determined, including the sample geometry and size, and the material preparation method; (2) understanding of fundamentals and procedures of the testing technique, for example, some techniques are limited to samples with specific geometries and some are limited to a specific range of thermophysical properties; and (3) understanding of the potential error sources which might affect the final results, for example, the convection and radiation heat losses.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2016;138(4):041001-041001-10. doi:10.1115/1.4034187.

Board-level physical test performance of CSP/BGA packages need in depth characterization of loading parameters and material behavioral properties. In recent years, many calibration methods were adopted by the researchers and industries to improvise solder joint performances of packages. Effective and uniform board response is one of the critical challenges in developing test board to qualify package components for solder joint reliability qualification. In this paper, an improvised board type alternative to standard Joint Electron Device Engineering Council (JEDEC) board is developed for uniform stress/strain response. An axis symmetrical board is chosen in comparison to the current JEDEC board. The effectiveness of the two boards are compared with each other under extreme banding under controlled drop test simulation. The uniform stress–stain distribution is recorded maintaining the no-ring phenomenon by selecting optimal shock pulse parameters. Selected impact/shock pulse is decided by identifying the maximum impact energy absorbed by the board during the drop event. Board surface strain and stress data are captured 1–2 mm away near the components are quantified for higher strain rate. The board local strain rate on the board surface is recorded at a selected time-step to quantify the dynamic stresses along the component side surface on the board. The simulation is performed by using ANSYS software using implicit method. Both linear SOLID45 and quadratic SOLID95 elements are used to compare and correlate the results. Close forms of results were correlated with the previous theoretical results.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041002-041002-6. doi:10.1115/1.4034369.

We propose a new approach to the modular packaging of microfluidic components, in which different functional components are not only fabricated separately but are also designed to be individually removable for the purposes of replacement or subsequent analysis. In this paper, we demonstrate one such component: a stand-alone microfluidic filter that can be custom-fabricated and then connected, disconnected, and replaced on a microfluidic chip as needed. This filter is also designed such that particles captured on the filter can be further analyzed or processed directly on the filter itself—for example, for microscopic examination or cell culturing. The filter is a thin (1 μm) transparent silicon nitride membrane that can be designed and fabricated according to specifications for different applications. This material is suitable for microscale fabrication; filtration of a variety of solutions, including biological samples; and subsequent particle imaging and processing. The porous nature of the thin filter allows for particle separation under relatively low pressures, thus protecting the particles from rupture or membrane damage. We describe two methods for integrating the filter apparatus onto a microfluidic chip such that it can be inserted, removed, and replaced. To demonstrate the utility of this approach, we fabricated custom-designed silicon-based filters, incorporated them onto microfluidic systems then filtered microparticles and live cells from test solutions, and finally removed the filters to image the microparticles and culture the cells directly on the filter membranes.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041003-041003-8. doi:10.1115/1.4034454.

A blister testing procedure combined with a numerical procedure can be used effectively for characterizing the adhesion strength. A challenge arises when it is implemented after subjecting samples to various environmental conditions. The concept of pseudoproperty is introduced to cope with the problem associated with property changes during environmental testing. The pseudoproperty set is determined directly from a deflection versus pressure curve obtained from a typical blister test. A classical energy balance approach is followed to evaluate the energy release rate from the critical pressure and pseudoproperty set. The proposed approach is carried out for an epoxy/copper interface after subjecting samples to full moisture saturation and a high temperature storage condition. In spite of significant change in property, the energy release rates are calculated accurately without extra tests for property measurements.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041004-041004-9. doi:10.1115/1.4034751.

In this study, a smart heat pump, which could be used for the cooling of electronics, made of laminated structure of thermoelectric (TE) and electrocaloric (EC) materials, is studied. A simple arrangement of two TE layers sandwiched with one EC layer is modeled. This smart heat pump utilized the newly developed EC materials of giant adiabatic temperature change and the TE materials of high figure of merit. The system has the advantages of no moving parts, made of solid state, operable over large working temperature difference, and can be formed into very small size. The operation of the device is numerically modeled considering the three major parametric effects: EC operation as a function of time, electric current applied on TE, and temperature difference between the hot and cold sinks. The results on coefficient of performance (COP) and heat flow per unit area are discussed. This study is performed as an early attempt of analyzing the basic physical features of TE–EC–TE laminated structure heat pump and extends the understanding by further discussing the tradeoff between lower COP and larger overall temperature difference coverage in the TE/EC hybrid heat pump system with multilaminated structure.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041005-041005-5. doi:10.1115/1.4034819.

The sandwich structure Cu/Sn/Cu solder joints with different thicknesses of the solder layers (δ) are fabricated using a reflow solder method. The microstructure and composition of the solder joints are observed and analyzed by scanning electron microscopy (SEM). Results show that the thickness of intermetallic compound (IMC) and Cu concentration in the solder layers increase with the decrease of δ after reflow. During thermal aging, the thickness of IMC does not increase according to the parabolic rule with the increase of aging time; the solder joint thickness affects markedly the growth rate of IMC layer. At the beginning of thermal aging, the growth rate of IMC in the thinner solder joints (δ ≤ 25 μm) is higher than that in the thicker ones (δ ≥ 30 μm). The growth rate of IMC (δ ≤ 25 μm) decreases in the thinner solder joints, while increases in the thicker solder joints (δ ≥ 40 μm) and is nearly invariable when the δ equals to 30 μm with aging time extending. The growth rate of IMC increases first and then decreases after reaching a peak value with the increase of δ in the later stage during aging. The main control element for IMC growth transfers from Cu to Sn with the reduction of size.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041006-041006-5. doi:10.1115/1.4034842.

Growth behavior of the intermetallic compound (IMC), FeSn2, was investigated in the liquid Sn/solid Fe reaction couple over the annealing temperatures from 250 °C to 400 °C. Low-carbon steel AISI 1018 was chosen to make Fe samples. The morphology and thickness of the IMC formed between Sn and Fe were examined using scanning electron microscopy (SEM). In addition, energy-dispersive X-ray spectroscopy (EDX) and X-ray diffraction (XRD) were used to confirm that the IMC is FeSn2. The growth kinetics of FeSn2 was modeled by parabolic law and empirical power law. Based on the models, the growth constants, the activation energy, and the time exponents were established at different annealing temperatures. It was found that the time exponent values obtained by fitting with empirical power law deviate from 0.5, meaning that volume (bulk) diffusion is not the only rate-controlling process in the liquid Sn/solid Fe reaction couple. Also, a variation in the time exponent values is indicative that the growth behavior is correlated with grain size growth and irregular grain morphology at different annealing stages. The results of this research show that AISI 1018 steel can readily react with Sn to form IMC on the interface. This is an essential requirement of soldering action using Sn-rich solders.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041007-041007-11. doi:10.1115/1.4034854.

With the growth and acceptance of liquid immersion cooling as a viable thermal management technique for high performance microelectronics, fundamental questions regarding the nature of the flow within the system will need to be addressed. Among these are how the coolant is directed toward components of primary interest as well as how other elements within the electronics package may affect the delivery of fluid to these more critical locations. The proposed study seeks to experimentally address these issues with particle image velocimetry (PIV) measurements of unheated and heated flow within an electronics enclosure. The effectiveness of three flow distribution designs at delivering coolant to elements of importance, in this case 6.45 cm2 (1 in.2) components meant to simulate processor chips, has been examined using the vectors yielded by the PIV experimentation in a control surface analysis around these critical components. While these previous scenarios are unheated, two-phase PIV has also been conducted with FC-72 as the working fluid while boiling is taking place. A control surface analysis around all four heated elements within the enclosure shows an expected roughly monotonic increase in the net liquid flow rate to the boiling elements as the power applied to them is increased. Additionally, discretized mapping of how the fluid is entering the area surrounding these boiling elements has been constructed to offer insight into how passive elements should be placed within an electronics enclosure so as to not obstruct or hinder the vital flow of coolant to the most critical components.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041008-041008-10. doi:10.1115/1.4034856.

In this paper, a lattice Boltzmann method (LBM)-based model is developed to simulate the subcontinuum behavior of multidimensional heat conduction in solids. Based on a previous study (Chen et al., 2014, “Sub-Continuum Thermal Modeling Using Diffusion in the Lattice Boltzmann Transport Equation,” Int. J. Heat Mass Transfer, 79, pp. 666–675), phonon energy transport is separated to a ballistic part and a diffusive part, with phonon equilibrium assumed at boundaries. Steady-state temperature/total energy density solutions from continuum scales to ballistic scales are considered. A refined LBM-based numerical approach is applied to a two-dimensional simplified transistor model proposed by (Sinha et al. 2006, “Non-Equilibrium Phonon Distributions in Sub-100 nm Silicon Transistors,” ASME J. Heat Transfer, 128(7), pp. 638–647), and the results are compared with the Fourier-based heat conduction model. The three-dimensional (3D) LBM model is also developed and verified at both the ballistic and continuous limits. The impact of film thickness on the cross-plane and in-plane thermal conductivities is analyzed, and a new model of the supplementary diffusion term is proposed. Predictions based on the finalized model are compared with the existing in-plane thermal conductivity measurements and cross-plane thermal conductivity molecular dynamics (MD) results.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041009-041009-10. doi:10.1115/1.4034927.

Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(4):041010-041010-10. doi:10.1115/1.4034861.

Thermoelectric coolers (TECs) are solid-state cooling devices that operate on the Seebeck effect. They can be used in electronic cooling applications as well as other refrigeration systems. Among the various factors that affect TEC performance within a system, it has been shown that the thermal conductance is an important parameter, which can also be easily altered during the design of a TEC to deliver optimal TEC performance for a given application. However, these studies have considered only a fixed heat load and heat sink temperature, whereas in many realistic applications these quantities can vary. A procedure has been developed for optimizing the thermal conductance of a TEC based on a typical operating cycle of time-varying heat load and sink temperature, while permitting constraints that ensure that one or more worst-case operating conditions can also be met. This procedure is valid for any arbitrary heat load and sink temperature functions; however, for illustrative purposes, a simple heat load function at fixed sink temperature (and a sink temperature function at fixed heat load) is used. The results show that the optimal conductance can strongly depend on the operating cycle, and the corresponding reduction in electrical input work (and corresponding increase in net coefficient of performance (COP)) can be significant.

Commentary by Dr. Valentin Fuster