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IN THIS ISSUE

### Review Article

J. Electron. Packag. 2016;138(2):020801-020801-22. doi:10.1115/1.4032984.
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Stretchable thin film materials have promising applications in many areas, including stretchable electronics, precision metrology, optical gratings, surface engineering, packaging, energy harvesting, and storage. They are usually realized by engineering geometric patterns and nonlinear mechanics of stiff thin films on compliant substrates, such as buckling of thin films on soft substrates, prefabricated wavy forms of thin films, and mesh layouts that combine structured islands and bridges. This paper reviews fabrication, application, and mechanics of stretchable thin film materials. Methods and fabrication processes of realizing stretchability in different thin films, such as semiconductors, metals, and polymers, on compliant substrates are introduced. Novel applications that are enabled by stretchable thin films are presented. The underlying mechanics of stretchable thin film materials in different systems is also discussed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):020802-020802-15. doi:10.1115/1.4033000.
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Polymers can be used as temporary place holders in the fabrication of embedded air gaps in a variety of electronic devices. Embedded air cavities can provide the lowest dielectric constant and loss for electrical insulation, mechanical compliance in devices where low-force deformations are desirable, and can temporarily protect movable parts during processing. Several families of polymers have been used as sacrificial, templating polymers including polycarbonates, polynorbornenes (PNBs), and polyaldehydes. The families can be distinguished by chemical structure and decomposition temperature. The decomposition temperature ranges from over 400 °C to below room temperature in the case of low ceiling temperature polymers. Overcoat materials include silicon dioxide, polyimides, epoxy, and bis-benzocyclobutene (BCB). The methods of air-gap fabrication are discussed. Finally, the use of photoactive compounds in the patterning of the sacrificial polymers is reviewed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):020803-020803-13. doi:10.1115/1.4033143.
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Recent years, semiconductor quantum dots (QDs) have attracted tremendous attentions for their unique characteristics for solid-state lighting (SSL) and thin-film display applications. The pure and tunable spectra of QDs make it possible to simultaneously achieve excellent color-rendering properties and high luminous efficiency (LE) when combining colloidal QDs with light-emitting diodes (LEDs). Due to its solution-based synthetic route, QDs are impractical for fabrication of LED. QDs have to be incorporated into polymer matrix, and the mixture is dispensed into the LED mold or placed onto the LED to fabricate the QD–LEDs, which is known as the packaging process. In this process, the compatibility of QDs' surface ligands with the polymer matrix should be ensured, otherwise the poor compatibility can lead to agglomeration or surface damage of QDs. Besides, combination of QDs–polymer with LED chip is a key step that converts part of blue light into other wavelengths (WLs) of light, so as to generate white light in the end. Since QD-LEDs consist of three or more kinds of QDs, the spectra distribution should be optimized to achieve a high color-rendering ability. This requires both theoretical spectra optimization and experimental validation. In addition, to prolong the reliability and lifetime of QD-LEDs, QDs have to be protected from oxygen and moisture penetration. And the heat generation inside the package should be well controlled because high temperature results in QDs' thermal quenching, consequently deteriorates QD-LEDs' performance greatly. Overall, QD-LEDs' packaging and applications present the above-mentioned technical challenges. A profound and comprehensive understanding of these problems enables the advancements of QD-LEDs' packaging processes and designs. In this review, we summarized the recent progress in the packaging of QD-LEDs. The wide applications of QD-LEDs in lighting and display were overviewed, followed by the challenges and the corresponding progresses for the QD-LEDs' packaging. This is a domain in which significant progress has been achieved in the last decade, and reporting on these advances will facilitate state-of-the-art QD-LEDs' packaging and application technologies.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):020804-020804-13. doi:10.1115/1.4033069.
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Sintered silver joint is a porous silver that bonds a semiconductor die to the substrate as part of the packaging process. Sintered Ag is one of the few possible bonding methods to fulfill the operating conditions of wide band-gap (WBG) power device technologies. We review the current technology development of sintered Ag as a bonding material from the perspective of patents filed by various stakeholders since late 1980s. This review addresses the formulation of sintered pastes (i.e., nano-Ag, hybrid Ag, and micron Ag fillers), innovations in the process and equipment to form this Ag joint. This review will provide the insights and confidence to engineers, scientists from universities and industry as well as investors who are developing and commercializing the sintered Ag as a bonding material for microelectronic packaging.

Commentary by Dr. Valentin Fuster

### Research Papers

J. Electron. Packag. 2016;138(2):021001-021001-8. doi:10.1115/1.4032880.

A series of dwell-fatigue tests were conducted on nanosilver sintered lap shear joint at elevated temperatures from 125 °C to 325 °C. The effects of temperature and loading conditions on dwell-fatigue behavior of nanosilver sintered lap shear joint were systematically studied. With higher temperature and longer dwell time, creep played a more important part in dwell-fatigue tests. Creep strain accumulated during maximum shear stress hold was found partly recovered by the subsequent cyclic unloading. Both the fracture mode and silver particle growth pattern were characterized by X-ray tomography system and scanning electron microscope (SEM). The mean shear strain rate $γ˙m$ synthesized the effects of various factors, such as temperature, shear stress amplitude, mean shear stress, and dwell time, by which the fatigue and dwell-fatigue life of nanosilver sintered lap shear joint could be well predicted within a factor of two.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):021002-021002-9. doi:10.1115/1.4032881.

The behavior of lead-free solder alloys under realistic service conditions is still not well understood. Life prediction of solder joints relies on conducting accelerated tests and extrapolating results to service conditions. This can be very misleading without proper constitutive relations and without understanding the effects of cycling parameter variations common under realistic service conditions. It has been shown that the fatigue life depends on the inelastic work accumulation, independently of cycling-induced material property variations, which explains the breakdown of damage accumulation rules and allows the development of a modified Miner's rule. This paper discusses the interacting effects of strain rate and amplitude variations on solder joint fatigue life. Individual SnAgCu solder joints with two different Ag contents (SAC305 and SAC105) were tested in low cycling shear fatigue under single and varying amplitudes with different strain rates. Such a shear fatigue experiment allows the measurement of work accumulation and the evolution of solder deformation properties during cycling. The results showed that cycling with a lower strain rate at fixed amplitude causes more damage per cycle. Alternating between mild amplitude at a high strain rate and harsh amplitude at a low strain rate leads to ongoing increases in the rate of damage at the mild amplitude and thus relatively rapid failure. In comparing SAC305 with SAC105, the effect of strain rate on both alloys is almost the same, and SAC305 is still more fatigue resistant than SAC105 in varying amplitude cycling with any strain rate.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):021003-021003-5. doi:10.1115/1.4033165.

The phosphor dip-transfer coating method is simple and flexible for transferring a pre-analyzed volume of phosphor gel, which can be beneficial to the high angular color uniformity (ACU) of white light-emitting diodes (LEDs). The crux of this method is the volume control of the phosphor gel; however, the critical factors which influence the volume control remain unrevealed. In this paper, we concentrate on investigating the transferred volume in terms of three parameters: withdrawal speed, post radius, and dipping depth. Numerical simulations were carried out utilizing the volume of fluid (VOF) model combined with the dynamic mesh model. The experiments were also conducted on an optical platform equipped with a high-speed camera. The simulation results coincide well with the experimental results, with the maximum relative difference within 15%. The results show that the transferred volume increases with the increasing withdrawal speed and remains stable when the speed is greater than 1 mm/s, and it shows a linear relationship with the cube of post radius. And the transferred volume will increase with the dipping depth. Based on the experimental and numerically work, it is concluded that the volume of the pre-analyzed phosphor gel can be precisely obtained.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):021004-021004-8. doi:10.1115/1.4033109.

A printed circuit board (PCB) comprises a solid piece of dielectric material with embedded layers of current carrying metal traces and vias. Geometric features of these metal traces and vias in modern PCBs are highly nonuniform and complicated such that the card level or system level numerical simulations by using the actual trace and via geometries are computationally expensive. The present study investigates the effects of Joule heating in current carrying traces on the temperature distribution of PCBs by conducting one-way and two-way direct current (DC) electric and computational fluid dynamics (CFD) simulations. DC electric field simulations are performed to determine the power map of trace layers which are modeled as planar heat generating sources by using the temperature-dependent electrical conductivity of the metal trace. The power distribution varies with the implemented size and power thresholds. Thermal conductivity map of the PCB is determined by using the electronic computer-aided design (ECAD) images of the individual layers. By using these planar source and thermal conductivity maps, CFD simulations are conducted to determine the resulting temperature distribution on the board. A methodology is developed and applied to a sample, complex PCB, and the generated results are compared with those of the previous studies and conventional models. The computational data show that the temperature distributions over the PCB and its mounted components experience large variations based on the implemented thermal conductivity mapping and the Joule heating modeling technique.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):021005-021005-5. doi:10.1115/1.4033309.

Thermal performance for embedded two-phase cooling using dielectric coolant (R1234ze) is evaluated on a ∼20 mm × 20 mm large die. The test vehicles incorporate radial expanding channels with embedded pin fields suitable for through-silicon-via (TSV) interconnects of multidie stacks. Power generating features mimicking those anticipated in future generations of processor chips with eight cores are included. Initial results show that for the types of power maps anticipated, critical heat fluxes (CHFs) in “core” areas of at least 350 W/cm2 with at least 20 W/cm2 “background” heating in rest of the chip area can be achieved with less than 30 °C temperature rise over the inlet coolant temperature. These heat fluxes are significantly higher than those seen for relatively long parallel channel devices of similar base channel dimensions. Experimental results of flow rate, pressure drop, “device,” and coolant temperature are also provided for these test vehicles along with details of the test facility developed to properly characterize the test vehicles.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(2):021006-021006-7. doi:10.1115/1.4033106.

Temperature distribution is the key factor affecting the bonding quality in the glass/glass laser bonding process. In this work, the finite element method was used to establish three-dimensional (3D) numerical analysis model of the temperature field during bonding. Based on the result of the finite element analysis, the crucial parameters and their influences on the temperature distribution were discussed. In order to predetermine the necessary process parameter values for bonding, a nonlinear multiparameter fitting formula was established to predict the maximum temperature. The fitting model was validated experimentally by recording the maximum temperature during laser bonding via an infrared thermal imager.

Commentary by Dr. Valentin Fuster

### Technical Brief

J. Electron. Packag. 2016;138(2):024501-024501-5. doi:10.1115/1.4032932.

Three-dimensional (3D) structure with through silicon via (TSV) technology is emerging as a key issue in microelectronic packaging industry, and electrical reliability has become one of the main technical subjects for the TSV designs. However, criteria used for TSV reliability tests have not been consistent in the literature, so that the criterion itself becomes a technical argument. To this end, this paper first performed several different reliability tests on the testing packaging with TSV chains, then statistically analyzed the experimental data with different failure criteria on resistance increasing, and finally constructed the Weibull failure curves with parameter extractions. After comparing the results, it is suggested that using different criteria may lead to the same failure mode on Weibull analyses, and 65% of failed devices are recommended as a suitable termination for reliability tests.

Commentary by Dr. Valentin Fuster