J. Electron. Packag. 2016;138(1):010201-010201-2. doi:10.1115/1.4032748.

InterPACK 2015, the flagship conference of the ASME Electronic and Photonic Packaging Division held on July 6–9, 2015 in San Francisco, CA, is the premier international forum for the exchange of state-of-the-art knowledge in research, development, manufacturing, and applications of electronic packaging, MEMS, and NEMS. This is the first time that the InterPACK has been held jointly with the International Conference on Nanochannels, Microchannels, and Minichannels (ICNMM). Jointly organized and held, there was an outstanding technical program featuring more than 600 technical presentations in nine technical tracks. The Technical Track Committees comprise leading researchers and engineers from industrial companies, government laboratories, and academic institutions throughout the world. The nine tracks are: (1) Advanced Electronics and Photonics: Packaging, Interconnect, and Reliability, (2) Emerging Technology Frontiers, (3) MEMS and NEMS, (4) Thermal Management, (5) Thermal Management Using Microchannels, Jets, and Sprays, (6) Fundamentals of Thermal and Fluid Transport in Nano-, Micro-, and Mini-scales, (7) Advanced Fabrication and Manufacturing, (8) Energy, Health, and Water-Applications of Nano-, Micro-, and Mini-scale Devices, and (9) Advanced Electronics and Photonics, Packaging Materials, and Processing. At the end of the conference, each track chair was invited to recommend two papers from their track for this special section. All the recommended papers are again reviewed and some of them are selected for publication in this special section.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2016;138(1):010901-010901-13. doi:10.1115/1.4032490.

A fully dynamic model of a microchannel evaporator is presented. The aim of the model is to study the highly dynamic parallel channel instabilities that occur in these evaporators in more detail. The numerical solver for the model is custom-built and the majority of the paper is focused on detailing the various aspects of this solver. The one-dimensional homogeneous two-phase flow conservation equations are solved to simulate the flow. The full three-dimensional (3D) conduction domain of the evaporator is also dynamically resolved. This allows for the correct simulation of the complex hydraulic and thermal interactions between the microchannels that give rise to the parallel channel instabilities. The model uses state-of-the-art correlations to calculate the frictional pressure losses and heat transfer in the microchannels. In addition, a model for inlet restrictions is also included to simulate the stabilizing effect of these components. In the final part of the paper, validation results of the model are presented, in which the stability results of the model are compared with the existing experimental data from the literature. Next, a parametric study is performed focusing on the stabilizing effects of the solid substrate properties. It is found that increasing the thermal conductivity and thickness of the solid substrate has a strong stabilizing effect, while increasing the number of microchannels has a small destabilizing effect. Finally, representative dynamic results are also given to demonstrate some of the unique capabilities of the model.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010902-010902-10. doi:10.1115/1.4032346.

In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010903-010903-7. doi:10.1115/1.4032345.

Vapor chamber technologies offer an attractive approach for passive cooling in portable electronic devices. Due to the market trends in device power consumption and thickness, vapor chamber effectiveness must be compared with alternative heat spreading materials at ultrathin form factors and low heat dissipation rates. A test facility is developed to experimentally characterize performance and analyze the behavior of ultrathin vapor chambers that must reject heat to the ambient via natural convection. The evaporator-side and ambient temperatures are measured directly; the condenser-side surface temperature distribution, which has critical ergonomics implications, is measured using an infrared (IR) camera calibrated pixel-by-pixel over the field of view and operating temperature range. The high thermal resistance imposed by natural convection in the vapor chamber heat dissipation pathway requires accurate prediction of the parasitic heat losses from the test facility using a combined experimental and numerical calibration procedure. Solid metal heat spreaders of known thermal conductivity are first tested, and the temperature distribution is reproduced using a numerical model for conduction in the heat spreader and thermal insulation by iteratively adjusting the external boundary conditions. A regression expression for the heat loss is developed as a function of measured operating conditions using the numerical model. A sample vapor chamber is tested for heat inputs below 2.5 W. Performance metrics are developed to characterize heat spreader performance in terms of the effective thermal resistance and the condenser-side temperature uniformity. The study offers a rigorous approach for testing and analysis of new vapor chamber designs, with accurate characterization of their performance relative to other heat spreaders.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010904-010904-8. doi:10.1115/1.4032463.

Molecular dynamics (MDs) simulations have been performed to investigate the boiling phenomena of thin liquid film adsorbed on a nanostructured solid surface with particular emphasis on the effect of wetting condition of the solid surface. The molecular system consists of liquid and vapor argon and solid platinum wall. The nanostructures which reside on top of the solid wall have shape of rectangular block. The solid–liquid interfacial wettability, in other words whether the solid surface is hydrophilic or hydrophobic, has been altered for different cases to examine its effect on boiling phenomena. The initial configuration of the simulation domain comprises a three-phase system (solid platinum, liquid argon, and vapor argon), which was equilibrated at 90 K. After equilibrium period, the wall temperature was suddenly increased from 90 K to 250 K which is far above the critical point of argon and this initiates rapid or explosive boiling. The spatial and temporal variation of temperature and density as well as the variation of system pressure with respect to time were closely monitored for each case. The heat flux normal to the solid surface was also calculated to illustrate the effectiveness of heat transfer for different cases of wetting conditions of solid surface. The results show that the wetting condition of surface has significant effect on explosive boiling of the thin liquid film. The surface with higher wettability (hydrophilic) provides more favorable conditions for boiling than the low-wetting surface (hydrophobic), and therefore, the liquid argon responds quickly and shifts from liquid to vapor phase faster in the case of hydrophilic surface. The heat transfer rate is also much higher in the case of hydrophilic surface.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010905-010905-8. doi:10.1115/1.4032557.

The flow of microbubbles in millichannels with typical dimensions in the range of few millimeters offers a reduced pressure loss with simultaneous large specific contact surface. The transformation of pressure into kinetic energy creates secondary flow in micro-orifices, which results in continuous bubble dispersion. In this work, bubble flow through different orifices and channel modules with widths up to 7 mm are experimentally and numerically studied. The effect of the orifice dimensions on bubble sizes is evaluated for hydraulic diameters of 0.25–0.5 mm with different aspect ratios. To provide larger residence times of the generated dispersions in the reactor, several channel structures are analyzed to offer less coalescence. Volume flow rates of 10–250 mL/min are studied with various phase ratios. Bubble diameters are generated in the range of less than 0.1–0.7 mm with narrow size distributions depending on the entire flow rate. Opening angles of the orifices above 6 deg resulted in flow detachments and recirculation zones around the effluent jet. The first break-up point is shifted closer to the orifice outlet with increasing velocity and hydraulic diameter. The entire break-up region stays nearly constant for each orifice indicating stronger velocity oscillations acting on the bubble surface. Linear relation of smaller bubble diameters with larger energy input was identified independent from Reynolds number. Flow detachment and coalescence in bends were avoided by an additional bend within the curve based on systematically varied geometrical dimensions.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010906-010906-7. doi:10.1115/1.4032493.

We demonstrate the lid-integral silicon cold-plate topology as a way to bring liquid cooling closer to the heat source integrated circuit (IC). It allows us to eliminate one thermal interface material (TIM2), to establish and improve TIM1 during packaging, to use wafer-level processes, and to ease integration in first-level packaging. We describe the integration and analyze the reliability aspects of this package using modeling and test vehicles. To compare the impact of geometry, materials, and mechanical coupling on warpage, strains, and stresses, we simulate finite element models of five different topologies on an organic land-grid array (LGA) carrier. We measure the thermal performance in terms of thermal resistance from cold-plate base to inlet liquid and obtain 15 mm2 K/W at 30 kPa pressure drop across the package. We build two different topologies using silicon cold-plates and injection-molded lids. Gasket-attached cold-plates pass an 800 kPa pressure test, and direct-attached cold-plates fracture in the cold-plate. The results advise to use a compliant layer between cold-plate and manifold lid and promise a uniformly thick TIM1 layer in the Si–Si matched topology. The work shows the feasibility of composite lids with integrated silicon cold-plates in high heat flux applications.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010907-010907-12. doi:10.1115/1.4032655.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) dissipate high power densities which generate hotspots and cause thermomechanical problems. Here, we propose and simulate GaN-based HEMT technologies that can remove power densities exceeding 30 kW/cm2 at relatively low mass flow rate and pressure drop. Thermal performance of the microcooler module is investigated by modeling both single- and two-phase flow conditions. A reduced-order modeling approach, based on an extensive literature review, is used to predict the appropriate range of heat transfer coefficients associated with the flow regimes for the flow conditions. Finite element simulations are performed to investigate the temperature distribution from GaN to parallel microchannels of the microcooler. Single- and two-phase conjugate computational fluid dynamics (CFD) simulations provide a lower bound of the total flow resistance in the microcooler as well as overall thermal resistance from GaN HEMT to working fluid. A parametric study is performed to optimize the thermal performance of the microcooler. The modeling results provide detailed flow conditions for the microcooler in order to investigate the required range of heat transfer coefficients for removal of heat fluxes up to 30 kW/cm2 and a junction temperature maintained below 250 °C. The detailed modeling results include local temperature and velocity fields in the microcooler module, which can help in identifying the approximate locations of the maximum velocity and recirculation regions that are susceptible to dryout conditions.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010908-010908-6. doi:10.1115/1.4032347.

The purpose of this paper is to demonstrate the possibility to selectively tune the convective heat transfer coefficient in different sections of a heat sink by varying the density of microfeatures in order to minimize temperature gradients between discrete heat sources positioned along the flow path. Lifetime of power electronics is strongly correlated to the thermal management of the junction. Therefore, it is of interest to have constant junction temperatures across all devices in the array. Implementation of microfeature enhancement on the convective side improves the heat transfer due to an increase in surface area. Specific shapes such as micro-hydrofoils offer a reduced pressure drop allowing for combined improvement of heat transfer and flow performance. This study presents experimental results from an array of three discrete heat sources (20 × 15 mm) generating 100 W/cm2 and positioned in line along the flow path with a spacing of 10 mm between each of the sources. The heat sink was machined out of aluminum 6061, and micro-hydrofoils with a characteristic length of 500 μm were embedded in the cold plate. The cooling medium used is water at a flow rate of 3.6–13.4 g/s corresponding to a Reynolds number of 420–1575. It is demonstrated that the baseplate temperature can be maintained below 90 °C, and the difference between the maximum temperatures of each heat source is less than 6.7 °C at a heat flux of 100 W/cm2 and a water flow rate of 4.8 g/s.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010909-010909-9. doi:10.1115/1.4032348.

As thermal management techniques for three-dimensional (3D) chip stacks and other high-power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased. To reduce the computational costs and time in the thermal analysis of through-layer via (TXV) structures, much research to date has focused on defining effective anisotropic thermal properties for a pseudohomogeneous medium using isothermal boundary conditions. While such an approach eliminates the need to model heat flow through individual vias, the resulting properties are found to depend on the specific boundary conditions applied to a unit TXV cell. More specifically, effective properties based on isothermal boundary conditions fail to capture the local “microspreading” resistance associated with more realistic heat flux distributions and local hot spots on the surface of these substrates. This work assesses how the thermal microspreading resistance present in arrays of vias in interposers, substrates, and other package components can be properly incorporated into the modeling of these arrays. We present the conditions under which spreading resistance plays a major role in determining the thermal characteristics of a via array and propose methods by which designers can both account for the effects of microspreading resistance and mitigate its contribution to the overall thermal behavior of such substrate–via systems. Finite element modeling (FEM) of TXV unit cells is performed using commercial simulation software (ansys).

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010910-010910-9. doi:10.1115/1.4032496.

This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 μm and pin diameters of 90 μm and 30 μm. Single-phase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm2 to 470 W/cm2. The maximum heat transfer coefficient reached was 60 kW/m2 K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010911-010911-10. doi:10.1115/1.4032492.

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010912-010912-11. doi:10.1115/1.4032494.

The generation-to-generation information technology (IT) performance and density demands continue to drive innovation in data center cooling technologies. For many applications, the ability to efficiently deliver cooling via traditional chilled air cooling approaches has become inadequate. Water cooling has been used in data centers for more than 50 years to improve heat dissipation, boost performance, and increase efficiency. While water cooling can undoubtedly have a higher initial capital cost, water cooling can be very cost effective when looking at the true life cycle cost of a water-cooled data center. This study aims at addressing how one should evaluate the true total cost of ownership (TCO) for water-cooled data centers by considering the combined capital and operational cost for both the IT systems and the data center facility. It compares several metrics, including return-on-investment for three cooling technologies: traditional air cooling, rack-level cooling using rear door heat exchangers, and direct water cooling (DWC) via cold plates. The results highlight several important variables, namely, IT power, data center location, site electric utility cost, and construction costs and how each of these influences the TCO of water cooling. The study further looks at implementing water cooling as part of a new data center construction project versus a retrofit or upgrade into an existing data center facility.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010913-010913-7. doi:10.1115/1.4032462.

This study investigates the reliability of low melt alloys (LMAs) containing gallium (Ga), indium (In), bismuth (Bi), and tin (Sn) for the application as Thermal interface materials (TIMs). The analysis described herein involved the in situ thermal performance of the LMAs as well as performance evaluation after accelerated life cycle testing, which included high temperature aging at 130 °C and thermal cycling from −40 °C to 80 °C. Three alloys (75.5Ga & 24.5In, 100Ga, and 51In, 32.5Bi & 16.5Sn) were chosen for testing the thermal performance. Testing methodologies used follow ASTM D5470 protocols and the performance of LMAs is compared with some high-performing commercially available TIMs. Results show that LMAs can offer extremely low (<0.01 cm2 °C/W) thermal resistance compared to any commercial TIMs. The LMA–substrate interactions were explored using different surface treatments (copper and tungsten). Measurements show that depending on the substrate–alloy combinations, the proposed alloys survive 1500 hrs of aging at 130 °C and 1000 cycles from −40 °C to 80 °C without significant performance degradation. The obtained results indicate the LMAs are very efficient as TIMs.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):010914-010914-12. doi:10.1115/1.4032495.

Design rules for portable electronic device are continuously striving for thinner printed wiring assemblies (PWAs) and smaller clearances because of ever-increasing demand for functionality and miniaturization. As a result, during accidental drop and impact events, there is an increased probability of internal secondary impact between a PWA and adjacent internal structures. In particular, compared to the initial impact, acceleration pulses caused by contact during secondary impacts are typically characterized by significant increase of amplitudes and frequency bandwidth. The resonant response in the thickness direction of printed wiring boards (PWBs) (termed the dynamic “breathing mode” of response, in this study) acts as a mechanical bandpass filter and places miniature internal structures in some components (such as microelectromechanical systems (MEMS)) at risk of failure, if any of them have resonant frequencies within the transmitted frequency bandwidth. This study is the first part of a two-part series, presenting qualitative parametric insights into the effect of secondary impacts in a PWA. This first part focuses on analyzing the frequency spectrum of: (i) the impulse caused by secondary impact, (ii) the energy transmitted by the dynamic “breathing” response of multilayer PWBs, and (iii) the consequential dynamic response of typical structures with high resonant frequencies that are mounted on the PWB. Examples include internal deformable structures in typical surface mount technology (SMT) components and in MEMS components. The second part of this series will further explore the effects of the breathing mode of vibration on failures of various SMT components of different frequencies.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):011001-011001-6. doi:10.1115/1.4032029.

All solid-state lighting products produce heat which should be removed by use of a heat sink. Since the two mating surfaces of light emitting diode (LED) package and heat sink are not flat, a thermal interface material (TIM) must be applied between them to fill the gaps resulting from their surface roughness and lack of coplanarity. The application of a traditional TIM may squeeze out when pressure is applied to join the surfaces and hence a short circuit may result. To avoid such a problem, a thin solid film based TIM has been suggested. In this study, a zinc oxide (ZnO) thin film was coated on Cu substrates and used as the TIM. The ZnO thin film coated substrates were used as heat sink purposes in this study. The prepared heat sink was tested with 3 W green LED and the observed results were compared with the results of same LED measured at bare and commercial thermal paste coated Cu substrates boundary conditions. The influence of interface material thickness on total thermal resistance (Rth-tot), rise in junction temperature (TJ), and optical properties of LED was analyzed. A noticeable reduction in Rth-tot (5.92 K/W) as well as TJ (ΔTJ = 11.83 °C) was observed for 800 nm ZnO thin film coated Cu substrates boundary conditions when compared with bare and thermal paste coated Cu substrates tested at 700 mA. Change in TJ influenced the thermal resistance of ZnO interface material. Improved lux level and decreased correlated color temperature (CCT) were also observed with ZnO coated Cu substrates.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):011002-011002-10. doi:10.1115/1.4032349.

This paper investigates the formation and the growth of the intermetallic compound (IMC) layer at the interface between the Sn3.0Ag0.5Cu Pb-free solder and the Cu substrate during isothermal aging at 150 °C. We measure the thickness of the IMC layer and the roughness of the solder/IMC interface, and these two factors are assumed to control the tensile behavior of the solder joints. First, it utilizes the tensile tests of the aged solder joints for analyzing the effect of the IMC growth on the tensile behavior of the solder joints. Then, the microcracking behavior of the IMC layer is investigated by finite element method (FEM). In addition, qualitative numerical simulations are applied to study the effect of the IMC layer thickness and the solder/IMC interfacial roughness on the overall response and the failure mode of solder joints. The experimental results indicate that when the aging time increases, both the thickness and the roughness of the IMC layer have a strong influence on the strength and the failure mode of solder joints. The numerical simulation results suggest that the overall strength of solder joints is reduced when the IMC layer is thick and the solder/IMC interface is rough, and the dominant failure mode migrates to the microcracks within the IMC layer when the IMC layer is thick and the solder/IMC interface is flat.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;138(1):011003-011003-10. doi:10.1115/1.4032497.

An analytical solution using Ritz method for the electronic assembly vibration problem has been presented in detail. In this solution, a special treatment for plate-mounted-on-standoffs boundary conditions scheme was required, and hence described. Also, a simple equation for estimating ball grid array (BGA) solder joint axial stiffness was developed. The results of the analytical solution were validated with modal analysis measurements and finite element (FE) models data in terms of natural frequencies and mode shapes. Then, the analytical solution was used to estimate the most critical solder joint deformations and stresses. Finally, the so developed solution provided an effective tool to examine the effect of several geometric and material configurations of electronic package structure on the fatigue performance of electronic products under mechanical vibration loadings.

Commentary by Dr. Valentin Fuster

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