0


Review Article

J. Electron. Packag. 2015;137(4):040801-040801-19. doi:10.1115/1.4031326.
FREE TO VIEW

Data centers are mission critical facilities that typically contain thousands of data processing equipment, such as servers, switches, and routers. In recent years, there has been a boom in data center usage, leading their energy consumption to grow by about 10% a year continuously. The heat generated in these data centers must be removed so as to prevent high temperatures from degrading their reliability, which would cost additional energy. Therefore, precise and reliable thermal management of the data center environment is critical. This paper focuses on recent advancements in data center modeling and energy optimization. A number of currently available and developmental thermal management technology in data centers are broadly reviewed. Computational fluid dynamics (CFD) for raised-floor data centers, experimental measurements, containment systems, economizer cooling, hybrid cooling, and device level cooling are all thoroughly reviewed. The paper concludes with a summary and presents areas of potential future research, which are based on the holistic integration of workload prediction and allocation, and thermal management using smart control systems.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):040802-040802-9. doi:10.1115/1.4031481.
FREE TO VIEW

Three-dimensional (3D) stacked electronics present significant advantages from an electrical design perspective, ranging from shorter interconnect lengths to enabling heterogeneous integration. However, multitier stacking exacerbates an already difficult thermal problem. Localized hotspots within individual tiers can provide an additional challenge when the high heat flux region is buried within the stack. Numerous investigations have been launched in the previous decade seeking to develop cooling solutions that can be integrated within the 3D stack, allowing the cooling to scale with the number of tiers in the system. Two-phase cooling is of particular interest, because the associated reduced flow rates may allow reduction in pumping power, and the saturated temperature condition of the coolant may offer enhanced device temperature uniformity. This paper presents a review of the advances in two-phase forced cooling in the past decade, with a focus on the challenges of integrating the technology in high heat flux 3D systems. A holistic approach is applied, considering not only the thermal performance of standalone cooling strategies but also coolant selection, fluidic routing, packaging, and system reliability. Finally, a cohesive approach to thermal design of an evaporative cooling based heat sink developed by the authors is presented, taking into account all of the integration considerations discussed previously. The thermal design seeks to achieve the dissipation of very large (in excess of 500 W/cm2) background heat fluxes over a large 1 cm × 1 cm chip area, as well as extreme (in excess of 2 kW/cm2) hotspot heat fluxes over small 200 μm × 200 μm areas, employing a hybrid design strategy that combines a micropin–fin heat sink for background cooling as well as localized, ultrathin microgaps for hotspot cooling.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):040803-040803-17. doi:10.1115/1.4031602.
FREE TO VIEW

Thermal interface materials (TIMs) play a critical role in conventionally packaged electronic systems and often represent the highest thermal resistance and/or least reliable element in the heat flow path from the chip to the external ambient. In defense applications, the need to accommodate large differences in the coefficients of thermal expansion (CTE) among the packaging materials, provide for in-field reworkability, and assure physical integrity as well as long-term reliability further exacerbates this situation. Epoxy-based thermoplastic TIMs are compliant and reworkable at low temperature, but their low thermal conductivities pose a significant barrier to the thermal packaging of high-power devices. Alternatively, while solder TIMs offer low thermal interface resistances, their mechanical stiffness and high melting points make them inappropriate for many of these applications. Consequently, Defense Advanced Research Projects Agency (DARPA) initiated a series of studies exploring the potential of nanomaterials and nanostructures to create TIMs with solderlike thermal resistance and thermoplasticlike compliance and reworkability. This paper describes the nano-TIM approaches taken and results obtained by four teams responding to the DARPA challenge of pursuing the development of low thermal resistance of 1 mm2 K/W and high compliance and reliability TIMs. These approaches include the use of metal nanosprings (GE), laminated solder and flexible graphite films (Teledyne), multiwalled carbon nanotubes (CNTs) with layered metallic bonding materials (Raytheon), and open-ended CNTs (Georgia Tech (GT)). Following a detailed description of the specific nano-TIM approaches taken and of the metrology developed and used to measure the very low thermal resistivities, the thermal performance achieved by these nano-TIMs, with constant thermal load, as well as under temperature cycling and in extended life testing (aging), will be presented. It has been found that the nano-TIMs developed by all four teams can provide thermal interface resistivities well below 10 mm2 K/W and that GE's copper nanospring TIMs can consistently achieve thermal interface resistances in the range of 1 mm2 K/W. This paper also introduces efforts undertaken for next generation TIMs to reach thermal interface resistance of just 0.1 mm2 K/W.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2015;137(4):041001-041001-13. doi:10.1115/1.4030952.

This study aims at investigating a polymer-based air-gap creation method for the packaging of microelectromechanical systems (MEMS), and exploring the chemical composition of the polymer residue on the final package. Polymer-based air-gap formation utilizes thermal decomposition of a sacrificial polymer, poly(propylene carbonate) (PPC), encapsulated within an overcoat polymer. BCB (Cyclotene 4026-46) was used as the overcoat material because decomposition products of sacrificial polymer are able to permeate through it, leaving an embedded air-gap structure around the MEMS device. Size-compatibility and cleanliness of MEMS devices are important attributes of the polymer-based air-gap MEMS packaging approach. This study provides a framework for size-compatible and clean air-gap formation by selecting the type of PPC, optimizing thermal treatment steps, identifying air-gap formation options, assessing air-gap formation performance, and analyzing the chemical composition of the residue. The air-gap formation processes using photosensitive PPC films had at least twice the residue compared to processes using nonphotosensitive PPC films. The major contribution to the residue in photosensitive PPC films was from the photoacid generator (PAG), which was used to catalyze the thermal decomposition of the PPC. BCB is compatible with PPC, and provides mechanical stability during creation of the air-gaps. The polymer-based air-gaps provide a monolithic, low-cost, integrated circuit compatible MEMS packaging option.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):041002-041002-6. doi:10.1115/1.4031079.

Presently, air cooling is the most common method of thermal management in data centers. In a data center, multiple servers are housed in a rack, and the racks are arranged in rows to allow cold air entry from the front (cold aisle) and hot air exit from the back (hot aisle), in what is referred as hot-aisle-cold-aisle (HACA) arrangement. If the racks are kept in an open room space, the differential pressure between the front and back of the rack is zero. However, this may not be true for some scenarios, such as, in the case of cold aisle containment, where the cold aisle is physically separated from the hot data center room space to minimize cold and hot air mixing. For an under-provisioned case (total supplied tile air flow rate < total rack air flow rate) the pressure in the cold aisle (front of the rack) will be lower than the data center room space (back of the rack). For this case, the rack air flow rate will be lower than the case without the containment. In this paper, we will present a methodology to measure the rack air flow rate sensitivity to differential pressure across the rack. Here, we use perforated covers at the back of the racks, which results in higher back pressure (and lower rack air flow rate) and the corresponding sensitivity of rack air flow rate to the differential pressure is obtained. The influence of variation and nonuniformity in the server fan speed is investigated, and it is observed that with consideration of fan laws, one can obtain results for different average fan speeds with reasonable accuracy. The measured sensitivity can be used to determine the rack air flow rate with variation in the cold aisle pressure, which can then be used as a boundary condition in computational fluid dynamics (CFD)/rapid models for data center air flow modeling. The measured sensitivity can also be used to determine the change in rack air flow rate with the use of different types of front/back perforated doors at the rack. Here, the rack air flow rate is measured using an array of thermal anemometers, pressure is measured using a micromanometer, and the fan speed is measured using an optical tachometer.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):041003-041003-10. doi:10.1115/1.4031523.

Currently, intermetallics (IMCs) in the solder joint are getting much attention due to their higher volume fraction in the smaller thickness interconnects. They possess different mechanical properties compared to bulk solder. Large volume fraction of IMCs may affect the mechanical behavior, thermomechanical and mechanical fatigue life and reliability of the solder interconnects due to very brittle nature compared to solder material. The question that this study is seeking to answer is how degrading IMCs are to the thermomechanical reliability of the microbumps used in three-dimensional (3D) integrated circuits (ICs) where the microsolder bumps have only a few microns of bond thicknesses. Several factors such as “squeezed out” solder geometry and IMC thickness are studied through a numerical experiment. Fatigue life is calculated using Coffin–Manson model. Results show that, though undesirable because of high likelihood of creating short circuits, squeezed out solder accumulates less inelastic strains under thermomechanical cyclic load and has higher fatigue life. The results show that with the increase of IMCs thickness in each model, the inelastic strains accumulation per cycle increases, thus decreasing the fatigue life. The drop in fatigue life tends to follow an exponential decay path. On the other hand, it was observed that plastic strain range per cycle tends to develop rapidly in Cu region with the increase in IMC thickness which calls for a consideration of Cu fatigue life more closely when the microbump contains a higher volume fraction of the IMCs. Overall, by analyzing the results, it is obvious that the presence of IMCs must be considered for microsolder bump with smaller bond thickness in fatigue life prediction model to generate more reasonable and correct results.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):041004-041004-8. doi:10.1115/1.4031471.

This paper presents an integrated approach combining principal component analysis (PCA) and Taguchi methods to develop a ball grid array (BGA), gold (Au) wire bonding process with multiple quality characteristics optimization. Eight main process factors of BGA wire bonding technology are selected as the control factors for parameter design. They are the factor A (seating ultrasonic generator (USG)), factor B (TIP height), factor C (C/V), factor D (USG current), factor E (USG bond time), factor F (bond force), factor G (FS threshold), and factor H (FAB size). The quality characteristics of the process in the study, including the wire pull strength, the ball shear strength, the ball thickness difference, the ball size difference, and the percentage of the Au–Al intermetallic compound (IMC) are measured. The optimal process parameters that meet the requirements for multiple quality characteristics are A1B3C1D3E3F1G1H2. They are then used to be tested for verification. Experimental results confirm that the optimal process design indeed enhances the quality characteristics investigated. The analysis of variance (ANOVA) results also show that the most important control factors affecting the quality characteristics are factor B (TIP height), factor C (C/V), and factor G (FS threshold), which accounts for 72.34% of total process variance. Thus, they must be strictly monitored during processing.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):041005-041005-8. doi:10.1115/1.4031680.

First-level and second-level compliant interconnect structures are being pursued in universities and industries to accommodate the differential displacement induced by the coefficient of thermal expansion mismatch between the die and the substrate or between the substrate and the board. The compliant interconnects mechanically decouple the die from the substrate or the substrate from the board, and thus reduce the thermally induced stresses in the assembly. This paper presents drop-test experimental and simulation data for scaled-up prototype of compliant interconnects. The simulations were based on Input-G method and performed using ANSYS® finite element software for varying drop heights. In parallel to the simulations, scaled-up compliant polymer interconnects sandwiched between a polymer die and a polymer substrate were fabricated using three-dimensional (3D) printing, and this fabrication provides a quick low-cost alternative to cleanroom fabrication. The prototype of the assembly was subjected to drop tests from varying drop heights. The response of the assembly during drop testing was captured using strain gauges and an accelerometer mounted on the prototype. The data from the experiments were compared with the predictions from the simulations. Based on such simulations, significant insight into the behavior of compliant interconnects under impact loading was obtained, which could be used for reliable design of compliant interconnect under impact loading. Both the experimental and simulation data reveal that the compliant interconnects are able to reduce the strains that transfer from substrate to die by one-order.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2015;137(4):041006-041006-8. doi:10.1115/1.4031480.

Electronics driven at high currents may experience local hot spots, which may cause thermal degradation or even catastrophic failures. This common problem occurs at light-emitting diode (LED) chips and it is not easily observed by end-users. Driving over 700 mA over a 1 mm2 chip is expected to generate local temperature gradients. In addition, bonding failures at manufacturing or during operation (cracks, delamination, etc.) may also lead to local hot spots. Therefore, possible hot spots over an LED chip have turned attention to direct cooling with dielectric liquids comprises the current study. Computational and experimental studies have been performed to understand the impact of conduction and alternatively convection with various dielectric fluids to abate local hot spots in a multichip LED light engine. To capture the local temperature distributions over the LED light engine with a dome in the domain especially over the LED chip; first, computational models have been built with a commercial computational fluid dynamics (CFD) software. Later, attention has been turned into experimental validation by using a multichip high brightness LED (HB LED) light engine. An optothermal evaluation has been made at single and multiphase heat transfer modes with dielectric fluids (LS5252, HFE7000, and silicone oil, etc.) to compare with a series of CFD models and experimental studies. While multiphase liquid-cooled LED system has a better cooling performance but lower optical extraction, single-phase liquid-cooled LED system has shown a reasonable thermal performance with a 15% enhancement at light extraction.

Commentary by Dr. Valentin Fuster

Technical Brief

J. Electron. Packag. 2015;137(4):044501-044501-3. doi:10.1115/1.4031750.

This paper researches temporary bonding/debonding based on propylene carbonate (PPC). The highest shear strength of 4.1 MPa was achieved when pure PPC was used as bonding adhesive. Room temperature debonding methods were investigated and compared with thermal debonding. Chemical debonding at room temperature was realized for bonding with the pure PPC. Several different chemicals can be used for chemical debonding. A photo acid generator (PAG)-assisted debonding method was demonstrated at room temperature when PAG-loaded PPC (PAG-PPC) was used as bonding adhesive. The ultraviolet (UV) radiation was used to enhance the PAG-assisted debonding.

Commentary by Dr. Valentin Fuster

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In