0


RESEARCH PAPERS

J. Electron. Packag. 2005;127(2):77-85. doi:10.1115/1.1846067.

Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2005;127(2):86-90. doi:10.1115/1.1846062.

One of the most important issues whether anisotropic conductive film (ACF) interconnection technology is suitable to be used for flip chip on organic board applications is thermal cycling reliability. In this study, thermally induced deformations and warpages of ACF flip chip assemblies as a function of distance from neutral point (DNP) and ACF materials properties were investigated using in situ high sensitivity moiré interferometry. For a nondestructive failure analysis, scanning acoustic microscopy investigation was performed for tested assemblies. To elucidate the effects of ACF material properties and DNP on the thermal cycling reliability of ACF assembly, Weibull analysis for the lifetime estimation of ACF joint was performed, and compared with thermal deformations of ACF flip chip assembly investigated by moiré interferometry. Results indicate that the properties of ACF have a significant role in the thermal deformation and reliability performance during thermal cycling testing. Therefore, optimized ACF properties can enhance ACF package reliability during thermal cycling regime.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):91-95. doi:10.1115/1.1899165.

Pb-free soldering and the use of electrically conducive adhesives in the electronics industry are a segment of the global trend towards a lead-free environment. In comparison to lead-free solders, current commercial isotropic conductive adhesives are characterized by lower conductivity and need much more time for curing. Usually, a few minutes at 150°C are enough only for precuring. In this paper we describe the developed family of formulations with a curing time of several seconds at 150°C. There are single-component formulations, solvent-free type, prepared in a special way on the base of the common, accessible resins. They have very convenient handling properties; e.g., no drying on open screen during printing process. Viscosity depends on the resin and may be intentionally changed. Shelf life for all these formulations is about 12months at room temperature in closed containers. Refrigeration is not necessary. Unfortunately, the material needs the highest quality and purity of electronic grade silver fillers. The total permitted level of impurities is estimated as less than 10ppm. However, this is, rather, an advantage of the silver-filled adhesives.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2005;127(2):96-105. doi:10.1115/1.1846069.

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips. There are two parts in this study. One is to show that the two-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the two-parameter and three-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu lead-free solder paste on lead-free printed circuit boards under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu and 63 wt %Sn37 wt %Pb and under three different thermal cycling profiles, namely, 25↔75°C, 0↔100°C, and −25↔125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10 wt %Sn90 wt %Pb) solder columns of the CCGA package are provided and discussed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2005;127(2):106-112. doi:10.1115/1.1849235.

Surface Nusselt numbers, pressure coefficients, and flow visualizations are presented which are measured as a turbulent jet, with a fully developed velocity profile, impinges on the cylindrical pedestal and on the surrounding flat surface. Thermochromic liquid crystals and shroud-transient techniques are used to measure spatially resolved surface temperature distributions, which are used to deduce local Nusselt numbers. Dimensionless pedestal heights H/D are 0, 0.5, 1.0, and 1.5, the jet Reynolds number Re is 23,000, and the surface distance to nozzle diameter L/d ranges from 2 to 10. Local Nusselt numbers drastically increase with a radial distance away from the stagnation point on top of the pedestal for H/D values of 0.5, 1.0, and 1.5. These are partially due to the small flow recirculation zones present on top of the pedestal, and mixing associated with the separation of flow streamlines near the edge of the upper surface on the pedestal. Local Nusselt numbers are also augmented at flat surface locations corresponding to positions where shear layers reattach downstream of the pedestal. In general, augmentation magnitudes become more pronounced as H/D becomes smaller because of greater vortex influences. Corresponding local Nusselt numbers, beneath shear layer reattachment locations for H/D=0.5, are 35 to 80% higher than values measured at the same flat surface locations when no pedestals are employed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2005;127(2):113-119. doi:10.1115/1.1849236.

This paper presents the reliability of anisotropic conductive film (ACF) joint tested under reflow soldering and environmental test effect. The ACF joint behaved differently under different reflow soldering profiles. The lower reflow temperature resulted in more reliable ACF joints by maintaining low contact resistance. By contrast, high contact resistance was found in assemblies treated with higher reflow. Under humidity aging (85°C/85%RH), bumpless chips proved to be unreliable due to corrosion mechanism. Moreover, ACF had shown degradation in chemical and physical properties, including modulus reduction, Tg depression, polymer hydrolysis, and surface swelling after exposing to humidity aging. The deterioration in reliability of aged ACF joint during reflow process was mainly caused by hydroscopic swelling-induced stress of ACF.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):120-126. doi:10.1115/1.1876472.

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb8Sn2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):127-134. doi:10.1115/1.1871193.

This paper presents the results of an investigation of the thermal performance of a graphite foam thermosyphon evaporator and discusses the foam’s potential for use in the thermal management of electronics. The graphitized carbon foam used in this study is an open-cell porous material that consists of a network of interconnected graphite ligaments whose thermal conductivities are up to five times higher than copper. While the bulk graphite foam has a thermal conductivity similar to aluminum, it has one-fifth the density, making it an excellent thermal management material. Furthermore, using the graphite foam as the evaporator in a thermosyphon enables the transfer of large amounts of energy with relatively low temperature difference and without the need for external pumping. Performance of the system with FC-72 and FC-87 was examined, and the effects of liquid fill level, condenser temperature, and foam height, width, and density were studied. Performance with FC-72 and FC-87 was found to be similar, while the liquid fill level, condenser temperature, geometry, and density of the graphite foam were found to significantly affect the thermal performance. The boiling was found to be surface tension dominated, and a simple model based on heat transfer from the outer surface is proposed. As much as 149W were dissipated from a 1cm2 heated area.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):135-140. doi:10.1115/1.1869513.

In a finite element analysis, when localized behavior of a large model is of particular concern, generally one would refine the mesh until it captures the local solution adequately. Submodeling is an alternative way for solving this kind of problem. It provides a relatively accurate solution at a modest computational cost. For a valid submodeling analysis, the boundaries of the submodel should be sufficiently far away from local features so that St. Venant’s principle holds. Moreover, special treatments are required for solving problems that involve path-dependent characteristics. This paper presents a general procedure to perform submodeling analyses for path-dependent thermomechanical problems without a priori assumptions on the structural response. The procedure was benchmarked using a bimaterial strip and demonstrated through analyses on a bump chip carrier package assembly. The procedure is conducive to the numerical assessment of fatigue lives of electronic packages.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):141-146. doi:10.1115/1.1869511.

A microfluidic mixing device for microsystems with electroosmotic flow (EOF)-driven liquid pumping is proposed and examined experimentally and numerically. Microchannels with SiO2 or Al2O3 wall are fabricated by using surface micromachining technique, and the EOF velocity for each microchannel is measured. A sample device where part of the SiO2 wall is covered with a patterned Al2O3 thin film is fabricated to demonstrate the proposed flow pattern change. Results of numerical calculations suggest mixing enhancement effect.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):147-156. doi:10.1115/1.1869514.

Field reliability extrapolations from accelerated tests necessitate simulation of a variety of material behaviors under general loading conditions. The Hierarchical Incremental Single Surface (HiSS) yield function (Desai, C. S., 2001, Mechanics of Materials and Interfaces: The Disturbed State Concept, CRC Press, Boca Raton, FL.) has been applied extensively to a wide range of materials, from solders and silicon to ceramics and geotechnical materials, for simulating continuous-yield elastoplastic and elastoviscoplastic behavior. This work presents a continuous-yield function that avoids problems with HiSS for thermal and tensile loading. Validations are presented for eutectic PbSn data of Wang (Wang, Z., Desai, C.S., and Kundu, T., 2001, “Disturbed State Constitutive Modeling and Testing of Joining Materials in Electronic Packaging,” report to NSF for Materials Processing and Manufacturing Division Grant 9812686, University of Arizona, Tucson, AZ). Limitations on the range of validity of the elastoplastic and the Perzyna elastoviscoplastic formulations are discussed.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):157-163. doi:10.1115/1.1898338.

The failure modes of flip chip solder joints under high electrical current density are studied experimentally. Three different failure modes are reported. Only one of the failure modes is caused by the combined effect of electromigration and thermomigration, where void nucleation and growth contribute to the ultimate failure of the module. The Ni under bump metallization–solder joint interface is found to be the favorite site for void nucleation and growth. The effect of pre-existing voids on the failure mechanism of a solder joint is also investigated

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):164-171. doi:10.1115/1.1870016.

The purposes of the paper are to consider the failure phenomenon by delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process shows elastic and viscoelastic behaviors and to suggest the optimum design by the approaches of stress analysis and fracture mechanics. The model for analysis is the plastic Small Outline J-lead package with a dimpled diepad. On the package without a crack, the stress analysis is done and the possibility of delamination is considered. For the model fully delaminated between the chip and the dimpled diepad, J-integrals in low temperature and C(t)-integrals in high temperature are calculated for the various design variables and the fracture integrity is discussed. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):172-177. doi:10.1115/1.1869509.

The design and thermal performance of a synthetic-air-jet-based heat sink for high-power dissipation electronics is discussed. Each fin of a plate-fin heat sink is straddled by a pair of two-dimensional synthetic jets, thereby creating a jet ejector system that entrains cool ambient air upstream of the heat sink and discharges it into the channels between the fins. The jets are created by periodic pressure variations induced in a plenum by electromagnetic actuators. The performance of the heat sink is assessed using a thermal test die encased in a heat spreader that is instrumented with a thermocouple. The case-to-ambient thermal resistance under natural convection with the heat sink is 3.15°CW. Forced convection with the synthetic jets enables a power dissipation of 59.2W at a case temperature of 70°C, resulting in a case-to-ambient thermal resistance of 0.76°CW. The synthetic-jet heat sink dissipates 40% more heat compared to steady flow from a ducted fan blowing air through the heat sink. The synthetic jets generate a flow rate of 4.48 CFM through the heat sink, resulting in 27.8 W/CFM and thermal effectiveness of 0.62. The effect of fin length on the thermal resistance of the heat sink is discussed. Detailed measurements on an instrumented heat sink estimate that the average heat transfer coefficients in the channel flow between the fins is 2.5 times that of a steady flow in the ducts at the same Reynolds Number.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):178-184. doi:10.1115/1.1898339.

The paper presents a study on printed wiring board (PWB) warpage caused by the mechanical fastening of separable interconnects, known as land grid array (LGA) package assemblies. Out-of-plane displacement of the PWB were measured and characterized, as well as force-per-pin values of the LGA, and correlations were made between the two. Classical laminate theory was utilized to describe the warpage behavior of the assembly and a model was presented to solve the out-of-plane displacements. An overall assessment of the assembly was made and compared to the mechanical specification of the LGA.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2004;127(2):185-188. doi:10.1115/1.1899164.

The paper presents a study of creep behavior of a printed wiring board caused by the mechanical fastening of separable connector, known as a land grid array. Time-temperature superposition method was employed to predict the lifetime creep behavior. A low-cost testing method based on the ASTM D790 three-point bending procedure was developed to predict and characterize creep of polymeric materials under low temperature, low stress, and large elapsed times.

Commentary by Dr. Valentin Fuster

TECHNICAL BRIEF

J. Electron. Packag. 2004;127(2):189-192. doi:10.1115/1.1869510.

This paper presents an assessment of four die-strength testing configurations using finite element analysis. The simulation indicates that ring-on-ring configuration is the best because it generates a uniform stress field on a large die surface area. The four-point-bend configuration ranks second and the three-point-bend configuration is third. The pin-on-ring configuration is the worst because the stress gradient is severe in the central region. To minimize uncertainty in the loading positions, it is advised that loading rings or bars with small radii be used.

Commentary by Dr. Valentin Fuster

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In