J. Electron. Packag. 2000;123(2):105-111. doi:10.1115/1.1347996.

Active thermal control for electronics on Mars rovers imposes a serious penalty in weight, volume, power consumption, and reliability. Thus, we propose that thermal control be eliminated for future rovers. From a functional standpoint there is no reason that the electronics could not operate over the entire temperature range of the Martian environment, which can vary from a low of ≈−90°C to a high of ≈+20°C during the Martian night and day. The upper end of this range is well within that for conventional electronics. Although the lower end is considerably below that for which conventional—even high-reliability—electronics is designed or tested, it is well established that electronic devices can operate to such low temperatures. The primary concern is reliability of the overall electronic system, especially in regard to the numerous daily temperature cycles that it would experience over the duration of a mission on Mars. Accordingly, key reliability issues have been identified for elimination of thermal control on future Mars rovers. One of these is attachment of semiconductor die onto substrates and into packages. Die attachment is critical since it forms a mechanical, thermal, and electrical interface between the electronic device and the substrate or package. This paper summarizes our initial investigation of existing information related to this issue, in order to form an opinion whether die attachment techniques exist, or could be developed with reasonable effort, to withstand the Mars thermal environment for a mission duration of approximately one earth year. Our conclusion, from a review of literature and personal contacts, is that die attachment can be made sufficiently reliable to satisfy the requirements of future Mars rovers. Moreover, it appears that there are several possible techniques from which to choose and that the requirements could be met by judicious selection from existing methods using hard solders, soft solders, or organic adhesives. Thus, die attachment does not appear to be a roadblock to eliminating thermal control for rover electronics. We recommend that this be further investigated and verified for the specific hardware and thermal conditions appropriate to Mars rovers.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(2):112-119. doi:10.1115/1.1339821.

To address the requirement for prediction and understanding of airflow in forced convection cooled electronic systems, a detailed experimental investigation of the outlet flow of typical axial cooling fans has been performed. The flow is shown to be complex over much of the fans operational range, with significant radial and tangential velocities and regions with little or no flow. The effect of partially blocking a fan and running it at elevated temperatures are both shown to be significant. The effect of attaching a fan to an electronic system is then investigated. Flow drawn through a system is shown to be simple and well predicted by a standard CFD package. Flow blown into a system is far more complex, with large areas of recirculating flow, and less accuracy in the prediction. The paper gives valuable and novel design insight into forced cooling flows in electronic systems and shows that the industry is still some way from a reliable design method.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(2):120-126. doi:10.1115/1.1339822.

The case is made for the continued use of single valued thermal resistances for the prediction of component junction temperature, and, hence, reliability. These values are adjusted using empirically determined influence factors to account for thermal and aerodynamic interactions at board level. The paper presents measured values of influence factors for arrays of Plastic Quad Flat Packs (PQFPs) over a range of Reynolds numbers and with a series of board level obstacles modeling upstream passive components. The results are formulated into a novel set of design rules.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 1999;123(2):127-131. doi:10.1115/1.1339196.

As electronic packaging technology moving to the CSP, wafer level packaging, fine pitch BGA (ball grid array) and high density interconnections, the wireability of the PCB/substrate and soldering technology are as important as reliability issues. In this work, a comparison of elliptical/round pads of area array type packages has been studied for soldering, reliability, and wireability requirements. The objective of this research is to develop numerical models for predicting reflow shapes of solder joint under elliptical/round pad boundary conditions and to study the reliability issue of the solder joint. In addition, a three-dimensional solder liquid formation model is developed for predicting the geometry, the restoring force, the wireability, and the reliability of solder joints in an area array type interconnections (e.g., ball grid array, flip chip) under elliptical and round pad configurations. In general, the reliability of the solder joints is highly dependent on the thermal-mechanical behaviors of the solder and the geometry configuration of the solder ball. These reliability factors include standoff height/contact angle of the solder joint, and the geometry layout/material properties of the package. An optimized solder pad design cannot only lead to a good reliability life of the solder joint but also can achieve a better wireability of the substrate. Furthermore, the solder reflow simulation used in this study is based on an energy minimization engine called Surface Evolver and the finite element software ABAQUS is used for thermal stress/strain nonlinear analysis.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(2):132-140. doi:10.1115/1.1339197.

The goals of the present paper are to apply the recently developed decomposed analysis procedure using a computer code developed in this study. The decomposed technique enables one to determine the equilibrium configuration of electronic packages with significant computational efficiency at a reasonable accuracy. Further, it allows the independent analysis of the subsystems enabling “reusable” modules in a manner analogous to the object-oriented programming paradigm of modern computer languages. The code described here uses a nonlinear optimization procedure that ensures the approximate satisfaction of the balance of mechanical energy. The developed procedure is demonstrated on a variety of two- and three-dimensional hypothetical and “real-world” electronic packages. It is shown that with the use of the decomposed solution methodology, for a 225 I/O PBGA package, a speedup of nearly seven times is achieved at an accuracy loss in displacements of approximately 5.5 percent. It is also shown that the calculated peak shear displacements agree very well with experimental measurements made using laser moiré interferometry. Since the analysis procedure is independent of the number of solder interconnects, significantly larger time savings are expected for larger packages.

Commentary by Dr. Valentin Fuster


J. Electron. Packag. 2000;123(2):141-146. doi:10.1115/1.1328744.

In this paper, the authors present a stress analysis technique based on a novel nested finite element methodology (NFEM). The NFEM is similar in concept to an earlier proposed multi-domain Rayleigh-Ritz methodology (Ling, S., 1997, “A Multi-Domain Rayleigh-Ritz Method for Thermomechanical Stress Analysis of Surface Mount Interconnects in Electronic Assemblies,” Ph.D. dissertation, Univ., of Maryland), that is based on a nested multi-field displacement assumption. The nested multi-field displacement technique may be viewed as a localized cascading of the p-type refinement in conventional finite element analysis. The concept and formulation of NFEM are presented in this paper while the application of NFEM to analyze the viscoplastic stress-state in two popular surface mount electronic interconnect styles is presented in Part II of this series. To illustrate the concept of NFEM, the formulation and results are provided for a one-dimensional viscoplastic example.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2000;123(2):147-155. doi:10.1115/1.1328745.

The nested finite element methodology (NFEM) presented in Part I of this series, is used in this paper to analyze the viscoplastic stress-state in a flip-chip-on-board (FCOB) and a chip scale package subjected to temperature cycling loads. The results are validated with conventional finite element method (CFEM). An energy-partitioning (EP) damage model is used to predict cycles to failure, based on the energy densities obtained from NFEM and CFEM, and results are compared with experiments.

Commentary by Dr. Valentin Fuster


J. Electron. Packag. 2000;123(2):156-158. doi:10.1115/1.1348011.

Ortega, A., 1996, “Conjugate Heat Transfer in Forced Air Cooling of Electronic Components,” Air Cooling Technology for Electronic Equipment, S. Kim and S. Lee, eds., CRC Press, New York, pp. 107–114.Zebib,  A., and Wo,  Y. K., 1989, “ A two-dimensional conjugate heat transfer model for forced air cooling of an electronic device,” ASME J. Electron. Packag., JEPAE4111, pp. 41–45.97gJEPAE41043-7398Gorobets,  V. G., 1995, “ Local and global heat transfer performance of a plate fin with a low thermal conductivity coating,” Heat Transfer Research, HTREE726, Nos. 3–8, pp. 445–461.HTREE71064-2285Chen,  H., Lan,  Z., and Wang,  T. I., 1994, “ Study of conjugate conduction-laminar film condensation for a vertical plate fin,” Int. J. Heat Mass Transf., IJHMAK37, No. 16, pp. 2592–2597.ijhIJHMAK0017-9310Palisoc,  A., and Lee,  C. C., 1988, “ Thermal properties of the multilayer infinite plate structure,” J. Appl. Phys., JAPIAU64, No. 64, pp. 410–415.japJAPIAU0021-8979Lee,  C. C., Palisoc,  A., and Min,  Y., 1989, “ Thermal Analysis of Integrated Circuit Devices and Packages,” IEEE Trans. Compon., Hybrids, Manuf. Technol., ITTEDR12, No. 4, pp. 701–709.ittITTEDR0148-6411Lee,  C. C., Min,  Y., and Palisoc,  A., 1989, “ A General Integration Algorithm for the Inverse Fourier Transform of Four-Layer Infinite Plate Structures,” IEEE Trans. Compon., Hybrids, Manuf. Technol., ITTEDR12, No. 4, pp. 710–716.ittITTEDR0148-6411Lee, C. C., and Min, Y., 1991, “Thermal Modeling of Semiconductor Devices and Packages using Analytical Methods,” National Electronic Packaging and Production Conference, Anaheim, CA, Vol. 1, pp. 147–160.Cole,  K. D., 1997, “ Conjugate heat transfer from a small heated strip,” Int. J. Heat Mass Transf., IJHMAK40, No. 11, pp. 2709–2719.ijhIJHMAK0017-9310Harman, S. A., 1998, “Conjugate heat transfer: the effects of axial conduction and the two component wall,” M. S. thesis, University of Nebraska, Lincoln, NE.

Commentary by Dr. Valentin Fuster


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