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Research Papers

J. Electron. Packag. 2018;140(3):031001-031001-11. doi:10.1115/1.4039790.

The aim of this paper is to model moisture ingress into a closed electronic enclosure under isothermal and non-isothermal conditions. As a consequence, an in-house code for moisture transport is developed using the Resistor-Capacitor (RC) method, which is efficient as regards computation time and resources. First, an in-house code is developed to model moisture transport through the enclosure walls driven by diffusion, which is based on the Fick's first and second law. Thus, the model couples a lumped analysis of moisture transport into the box interior with a modified one-dimensional (1D) analogy of Fick's second law for diffusion in the walls. Thereafter, under non-isothermal conditions, the moisture RC circuit is coupled with the same configuration of thermal RC circuit. The paper concerns the study of the impact of imperfections in the enclosure for the whole diffusion process. Moreover, a study of the impact of wall thickness, different diffusion coefficient, and initial conditions in the wall for the moisture transport is accomplished. Comparison of modeling and experimental results showed that the RC model is very applicable for simple and rough enclosure design. Furthermore, the experimental and modeling results indicate that the imperfections, with certain limits, do not have a significant effect on the moisture transport. The modeling of moisture transport under non-isothermal conditions shows that the internal moisture oscillations follow ambient temperature changes albeit with a delay. Although, moisture ingress is slightly dependent on ambient moisture oscillations; however, it is not so dominant until equilibrium is reached.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(3):031002-031002-8. doi:10.1115/1.4039861.

This paper details the fabrication and testing of a combined temperature and expansion sensor to improve state of charge (SOC) and state of health (SOH) estimation for Li-ion batteries. These sensors enable the characterization of periodic stress and strain changes in the electrode materials of Lithium-ion batteries during the charge and discharge process. These ultrathin sensors are built on a polyimide substrate which can enable direct integration between cells without compromising safety or cell cooling design. Leveraging the sensor design and fabrication process used to create inductive coil eddy current (EC) sensors for crack detection, these sensors were characterized on three Panasonic 5 A-h cells showing the capability to measure expansion of Li-ion batteries. By sensing the intercalation effects, which cause cell expansion, improvements in estimation of SOH and SOC can be enabled through the use of physics-based battery models, which combine the thermal, mechanical, and electrochemical aspects of its operation.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(3):031003-031003-10. doi:10.1115/1.4039264.

The increasing heat densities in electronic components and focus on energy efficiency have motivated utilization of embedded two-phase cooling, which reduces system-level thermal resistance and pumping power. To achieve maximum benefit, high heat fluxes and vapor qualities should be achieved simultaneously. While many researchers have achieved heat fluxes in excess of 1 kW/cm2, vapor qualities are often below 10%, requiring a significantly large amount of energy spent on subcooling or pumping power, which minimizes the benefit of using two-phase thermal transport. In this work, we describe our recent work with cooling devices utilizing film evaporation with an enhanced fluid delivery system (FEEDS). The design, calibration, and experimental testing of a press-fit and bonded FEEDS test section are detailed here. Heat transfer and pressure drop performance was characterized and discussed. With the press-fit Si test chip, heat fluxes in excess of 1 kW/cm2 were obtained at vapor qualities approaching 45% and a coefficient of performance (COP) approaching 1400. With the bonded SiC test chip, heat fluxes in excess of 1 kW/cm2 were achieved at a vapor quality of 85% and heat densities approaching 490 W/cm3.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(3):031004-031004-6. doi:10.1115/1.4040002.

The diamond abrasive process which is applied onto the silicon wafer edge, the so called “edge trimming,” is an important step in three-dimensional microelectronics processing technology, due to the significant thickness reduction of the wafer after thinning. Nevertheless, the wafer edge defects caused by edge trimming have often been overlooked. Although the mechanisms of the formation of the defects in Si due to trimming may be similar to the ones caused by grinding, an in-depth study and risk assessment have not been done yet. In addition, the variety of stress relief processing options can give different morphology and defect removal behavior on the edge trimmed Si sidewall. In a first study, we used transmission electron microscopy and Raman spectroscopy to analyze the defects caused by edge trimming. We show the presence of a continuous layer of amorphous Si and of different phases of Si, caused by edge trimming. A comparison of the damage induced in the Si by two different integration schemes is also discussed. When polishing is used for stress release, the observed sidewall defects stay, since the polishing force is only applied on the top surface of the wafer. On the other hand, the damage is completely removed for the case of wet and dry etching. The surface chemical reactions occurring at the surface during these processes are also acting on the Si sidewall. These findings provide a workable edge trimming and stress relief method for permanently bonded wafers, with many industrial applications.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(3):031005-031005-9. doi:10.1115/1.4040105.

Solder joints in electronic assemblies are subjected to mechanical and thermal cycling. These cyclic loadings lead to the fatigue failure of solder joints involving damage accumulation, crack initiation, crack propagation, and failure. Aging leads to significant changes on the microstructure and mechanical behavior of solder joints. While the effect of thermal aging on solder behavior has been examined, no prior studies have focused on the effect of long-term room temperature aging (25 °C) on the solder failure and fatigue behavior. In this paper, the effects of long-term room temperature aging on the fatigue behavior of five common lead-free solder alloys, i.e., SAC305, SAC105, SAC-Ni, SAC-X-Plus, and Innolot, have been investigated. Several individual lead-free solder joints on printed circuited boards with two aging conditions (no aging and 4 years of aging) have been prepared and subjected to shear cyclic stress–strain loadings until the complete failure. Fatigue life was recorded for each solder alloy. From the stress–strain hysteresis loop, inelastic work and plastic strain ranges were measured and empirically modeled with the fatigue life. The results indicated that 4 years of room temperature aging significantly decreases the fatigue life of the solder joints. Also, inelastic work per cycle and plastic strain range are increased after 4 years of room temperature aging. The fatigue life degradation for the solder alloys with doped elements (Ni, Bi, Sb) was relatively less compared to the traditional SAC105 and SAC305.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(3):031006-031006-8. doi:10.1115/1.4040204.

We have investigated a novel hybrid nanocomposite thermal interface material (TIM) that consists of silver nanoparticles (AgNPs), silver nanoflakes (AgNFs), and copper microparticles (CuMPs). Continuous metallic network form while AgNPs and AgNFs fuse to join bigger CuMPs upon hot compression, resulting in superior thermal and mechanical performances. The assembly temperature is as low as 125 °C due to the size effect of silver nanoparticulates. The thermal conductivity, k, of the hybrid nanocomposite TIMs is found to be in the range of 15–140 W/mK, exceeding best-performing commercial thermal greases, while comparable to high-end solder TIMs. The dependence of k on the solid packing density and the volume fraction of voids is discussed through comparing to model predictions.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2018;140(3):031007-031007-5. doi:10.1115/1.4040298.

This study mainly focuses on site effects of the Ni pad interface on intermetallic compounds (IMCs) characteristic during assembly reflowing, and attempts to provide a reasonable explanation for this particular finding. Besides, the changes of the resulting IMCs characteristic are characterized during thermal shock (TS) cycling, and their potential influences on thermal–mechanical reliability of microjoints are evaluated experimentally and numerically. The results show that the site on the Ni pad interface of silicon chip has great influence on interfacial reaction products, i.e., interfacial IMCs. After bumps soldering, a great amount of larger diamond-shaped (Cu, Ni)6Sn5 compounds were densely packed at the edge region, while some smaller ones were only scattered at the center region. Moreover, substantial particle-shaped (Ni, Cu)3Sn4 compounds as well as some rod-shaped ones emerged at the spaces between the (Cu, Ni)6Sn5 compounds of the center region. More importantly, such site effects were remained in the microjoints during TS cycling, which induced the formation of larger protruding (Cu, Ni)6Sn5 compounds. Finite element (FE) simulation results showed that the stress was mainly concentrated at the top of the protruding (Cu, Ni)6Sn5 compounds, which can be a critical reason to cause the crack occurrence. Furthermore, the underlying mechanism of the interfacial IMCs characteristic induced by the site effects was attempted to propose during bumps soldering.

Commentary by Dr. Valentin Fuster

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