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Review Article

J. Electron. Packag. 2016;139(1):010801-010801-22. doi:10.1115/1.4035019.
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Thermal management of very large-scale computers will have to leave the traditional well-beaten path. Up to the present time, the primary concern has been with rising heat flux on the integrated circuit chip, while a space has been available for the implementation of high-performance cooling design. In future systems, the spatial constraint will become a primary determinant of thermal management methodology. To corroborate this perspective, the evolution of computer's hardware morphology is simulated. Simulation tool is the geometric model, where the model structure is composed of circuit cells and platforms for circuit blocks. The cell is the minimum circuit element whose size is pegged to the technology node, while the total number of cells represents the system size. The platforms are the models of microprocessor chips, multichip modules (MCMs), and printed wiring boards (PWBs). The major points of discussion are as follows: (1) The system morphology is dictated by the competition between the progress of technology node and the demand for increase in the system size. (2) Only where the miniaturization of cells is achieved so as to deploy a system on a few PWBs, ample space is created for thermal management. (3) In the future, the cell miniaturization will hit the physical limit, while the demand for larger systems will be unabated. Liquid cooling, where the coolant is driven through very long microchannels, may provide a viable thermal solution.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(1):010802-010802-11. doi:10.1115/1.4035598.
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Reliability issues associated with moisture have become increasingly important as advanced electronic devices are nowhere more evident than in portable electronic products. The transition to the Pb-free solders, which require higher reflow temperature, makes the problem further exacerbated. Moisture absorbed into semiconductor packages can initiate many failure mechanisms, in particular interfacial delamination, degradation of adhesion strength, etc. The absorbed moisture can also result in catastrophic crack propagation during reflow process, the well-known phenomenon called popcorning. High vapor pressure inside pre-existing voids at material interfaces is known to be a dominant driving force of this phenomenon. This paper reviews various existing mechanisms of water accumulation inside voids. The procedures to obtain the critical hygroscopic properties are described. Advanced numerical modeling schemes to analyze the moisture diffusion phenomenon are followed with selected examples.

Commentary by Dr. Valentin Fuster

Research Papers

J. Electron. Packag. 2016;139(1):011001-011001-11. doi:10.1115/1.4035064.

In this paper, thermal management in GaN (gallium nitride) based microelectronic devices is addressed using microfluidic cooling. Numerical modeling is done using finite element analysis (FEA), and the results for temperature distribution are presented for a system comprising multiple cooling channels underneath GaN high-electron mobility transistors (HEMTs). The thermal stack modeled is compatible for heterogeneous integration with conventional silicon-based CMOS devices. Parametric studies for cooling performance are done over a range of geometric and flow factors to determine the optimal cooling configuration within the specified constraints. A power dissipation of 2–4 W/mm is modeled along each HEMT finger in the proposed configuration. The cooling arrangements modeled here hold promising potential for implementation in high-performance radio-frequency (RF) systems for power amplifiers, transmission lines, and other applications in defense and military.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;139(1):011002-011002-8. doi:10.1115/1.4035025.

This work presents an experimental study to enhance the thermal contact conductance of high performance thermal interface materials (TIMs) using gallium alloy. In this experiment, the gallium alloy-based TIMs are synthesized by a micro-oxidation reaction method, which consists of gallium oxides (Ga2O3) dispersed uniformly in gallium alloys. An experimental apparatus is designed to measure the thermal resistance across the gallium alloy-based TIMs under steady-state conditions. The existence of Ga2O3 can effectively improve the wettability of gallium alloys with other materials. For example, they have a better wettability with copper and anodic coloring 6063 aluminum-alloy without any extrusion between the interface layers. Gallium binary alloy-based TIMs (GBTIM) or ternary alloy based-TIMs (GTTIM) are found to increase the operational temperature range comparing with that of the conventional thermal greases. The measured highest thermal conductivity is as high as 19.2 Wm−1K−1 for GBTIM at room temperature. The wide operational temperature, better wettability, and higher thermal conductivity make gallium alloy-based TIMs promising for a wider application as TIMs in electronic packaging areas. The measured resistance is found to be as low as 2.2 mm2 KW−1 for GBTIM with a pressure of 0.05 MPa, which is much lower than that of the best commercialized thermal greases. In view of controlling pollution and raw materials wasting, the gallium alloy-based TIMs can be cleaned by 30% NaOH solution, and the pure gallium alloys are recycled, which can satisfy industrial production requirements effectively.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;139(1):011003-011003-10. doi:10.1115/1.4035241.

Thermal ground planes (TGPs) are passive thermal management devices that utilize the phase-change of a working fluid to achieve high thermal conductivity and low thermal resistance. TGPs are flat, two-dimensional heat pipes—similar to vapor chambers—in which liquid is held within a capillary wick, and vapor is held in a sealed vapor layer. Heat is absorbed at an evaporator region, causing the liquid to evaporate. The heated vapor in the vapor core is carried via convection to a condenser region where it condenses as the heat is expelled from the TGP to an external heat sink. The condensed liquid is then pulled back to the evaporator via capillary forces in the wick. In numerous applications, mechanical flexibility of the TGP is required, as is low-cost manufacturing and viable integration routes with electronics. This work describes a flexible TGP (FTGP) fabricated using printed circuit board (PCB) technology, in which commercially available copper-cladded polyimide sheets are used as the casing material. The wick is composed of three layers of fine copper mesh electroplated or sintered together and coated with atomic layer deposited TiO2. A coarse nylon or polyether ether ketone (PEEK) mesh defines the vapor transport layer, and water is used as the working fluid. The perimeter of the device is heat-sealed with flouroethylene propylene (FEP), which has been found to provide a near-hermetic seal for several months and is suitable for flexible applications. This architecture allows the TGP to function with minimal reduction in heat transfer performance while bent by 90 deg, and full functionality is returned when the device is returned to its flat configuration. The FTGP's measured thermal resistance is about half that of an equivalent copper reference for input heat fluxes of 3–6 W/cm2. More than 30 copper-cladded polyimide FTGPs were fabricated and characterized using both simple qualitative and more involved quantitative test setups. The results show that the fabrication and assembly processes developed in this work are repeatable and the devices are durable.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2016;139(1):011004-011004-8. doi:10.1115/1.4035178.

Thermal interface materials (TIMs) constitute a critical component for heat dissipation in electronic packaging systems. However, the extent to which a conventional steady-state thermal characterization apparatus can resolve the interfacial thermal resistance across current high-performance interfaces (RT < 1 mm2⋅K/W) is not clear. In this work, we quantify the minimum value of RT that can be measured with this instrument. We find that in order to increase the resolution of the measurement, the thermal resistance through the instrument's reference bars must be minimized relative to RT. This is practically achieved by reducing reference bar length. However, we purport that the minimization of reference bar length is limited by the effects of thermal probe intrusion along the primary measurement pathway. Using numerical simulations, we find that the characteristics of the probes and surrounding filler material can significantly impact the measurement of temperature along each reference bar. Moreover, we find that probes must be spaced 15 diameters apart to maintain a uniform heat flux at the interface, which limits the number of thermal probes that can be used for a given reference bar length. Within practical constraints, the minimum thermal resistance that can be measured with an ideal instrument is found to be 3 mm2⋅K/W. To verify these results, the thermal resistance across an indium heat spring material with an expected thermal contact resistance of ∼1 mm2⋅K/W is experimentally measured and found to differ by more than 100% when compared to manufacturer-reported values.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(1):011005-011005-10. doi:10.1115/1.4035386.

Multi-microchannel evaporators are often used to cool down electronic devices subjected to continuous heat load variations. However, so far, rare studies have addressed the transient flow boiling local heat transfer data occurring in such applications. The present paper introduces and compares two different data reduction methods for transient flow boiling data in a multi-microchannel evaporator. A transient test of heat disturbance from 20 to 30 W cm−2 was conducted in a multi-microchannel evaporator using R236fa as the test fluid. The test section was 1 × 1 cm2 in size and had 67 channels, each having a cross-sectional area of 100 × 100 μm2. The micro-evaporator backside temperature was obtained with a fine-resolution infrared (IR) camera. The first data reduction method (referred to three-dimensional (3D)-TDMA) consists in solving a transient 3D inverse heat conduction problem by using a tridiagonal matrix algorithm (TDMA), a Newton–Raphson iteration, and a local energy balance method. The second method (referred to two-dimensional (2D)-controlled) considers only 2D conduction in the substrate of the micro-evaporator and solves at each time step the well-posed 2D conduction problem using a semi-implicit solver. It is shown that the first method is more accurate, while the second one reduces significantly the computational time but led to an approximated solution. This is mainly due to the 2D assumption used in the second method without considering heat conduction in the widthwise direction of the micro-evaporator.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(1):011006-011006-8. doi:10.1115/1.4035387.

As integration levels increase in next generation electronics, high power density devices become more susceptible to hotspot formation, which often imposes a thermal limitation on performance. Flow boiling of R134a in two microgap heat sink configurations was investigated as a solution for hotspot thermal management: a bare microgap and inline micro-pin fin populated microgap, both with 10 μm gap height, were tested in terms of their ability to dissipate heat fluxes approaching 5 kW/cm2 at the heat source. Additional parameters investigated include mass fluxes up to 3000 kg/m2 s at inlet pressures up to 1.5 MPa and exit qualities approaching unity. The microgap testbeds investigated consist of a silicon layer which is heated from the bottom using resistive heaters and capped with glass to enable visual observation of two-phase flow regimes. Wall temperature, device thermal resistance, and pressure drop results are presented and mapped to the dominant flow regimes that were observed in the microgap.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(1):011007-011007-8. doi:10.1115/1.4035596.

In a raised floor data center, cold air from a pressurized subfloor plenum reaches the data center room space through perforated floor tiles. Presently, commercial tool “Flow Hood” is used to measure the tile air flow rate. Here, we will discuss the operating principle and the shortcomings of the commercial tool and introduce two other tile air flow rate measurement tools. The first tool has an array of thermal anemometers (named as “Anemometric Tool”), and the second tool uses the principle of temperature rise across a known heat load to measure the tile air flow rate (named as “Calorimetric Tool”). The performance of the tools is discussed for different types of tiles for a wide range of tile air flow rates. It is found that the proposed tools result in lower uncertainty and work better for high porosity tiles, as compared to the commercial tool.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(1):011008-011008-9. doi:10.1115/1.4035597.

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(1):011009-011009-9. doi:10.1115/1.4035703.

Carbon has become an attractive material for electronic packaging applications, such as interconnects, because of its low density and reasonable electrical conductivity. One challenge in these applications is overcoming the inherent chemical incompatibility between carbon and metals that limits adhesion. Recently, we explored a new technique for electroplating carbon fibers with nickel. Electroplated carbon fiber tows were soldered to nickel metal tabs using SAC 305 (Sn3Ag0.5Cu). The electroplated nickel was found to be free of microvoids with (Ni,Cu)3Sn4 forming as intermetallic compounds (IMCs) in an annular region presumed to be Ni3Sn4 at the SAC 305-Ni interface. Mechanical characterization of the carbon fiber–nickel interface revealed bond strengths up to 434 N, which is similar to a 22 gauge high strength copper clad steel. Electrical resistances were found to be as low as 1.1 Ω for a 38.1 mm long connection. Carbon–metal connections prepared using silver epoxy were found to have 80% lower load bearing capacity and 10–20% higher electrical resistance. Battery discharge tests indicated that the carbon connections reduced performance by only 4% compared to conventional copper. The performance drop increased to 7% when the discharge time was increased by 50%, indicating some thermal dependence. The electroplating technique is a fairly simple and inexpensive means of enhancing the wettability of carbon fiber to create scalable carbon-based conductors for low current systems.

Commentary by Dr. Valentin Fuster

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