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J. Electron. Packag. 2017;139(2):021001-021001-7. doi:10.1115/1.4036065.

For thermal management architectures wherein the heat sink is embedded close to a dynamic heat source, nonuniformities may propagate through the heat sink base to the coolant. Available transient models predict the effective heat spreading resistance to calculate chip temperature rise, or simplify to a representative axisymmetric geometry. The coolant-side temperature response is seldom considered, despite the potential influence on flow distribution and stability in two-phase microchannel heat sinks. This study solves three-dimensional transient heat conduction in a Cartesian chip-on-substrate geometry to predict spatial and temporal variations of temperature on the coolant side. The solution for the unit step response of the three-dimensional system is extended to any arbitrary temporal heat input using Duhamel's method. For time-periodic heat inputs, the steady-periodic solution is calculated using the method of complex temperature. As an example case, the solution of the coolant-side temperature response in the presence of different transient heat inputs from multiple heat sources is demonstrated. To represent a case where the thermal spreading from a heat source is localized, the problem is simplified to a single heat source at the center of the domain. Metrics are developed to quantify the degree of spatial and temporal nonuniformity in the coolant-side temperature profiles. These nonuniformities are mapped as a function of nondimensional geometric parameters and boundary conditions. Several case studies are presented to demonstrate the utility of such maps.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):021002-021002-11. doi:10.1115/1.4036363.

Deployment of airside economizers (ASEs) in data centers is rapidly gaining acceptance to reduce cost of cooling energy by reducing hours of operation of computer room air conditioning (CRAC) units. Airside economization has associated risk of introducing gaseous and particulate contamination into data centers, thus degrading the reliability of information technology (IT) equipment. The challenge is to determine reliability degradation of IT equipment if operated in environmental conditions outside American Society of Heating, Refrigeration, and Air-Conditioning Engineers (ASHRAE) recommended envelope with contamination severity levels higher than G1. This paper is a first attempt at addressing this challenge by studying the cumulative corrosion damage to IT equipment operated in an experimental modular data center (MDC) located in an industrial area with measured level of air contaminants in ISA severity level G2. This study serves several purposes including: correlating IT equipment reliability to levels of airborne corrosive contaminants and studying degree of reliability degradation when IT equipment is operated outside ASHRAE recommended envelope at a location with high levels of contaminants. Reliability degradation of servers exposed to outside air via an airside economizer was determined qualitatively by examining corrosion of components in these servers and comparing the results to corrosion of components in other similar servers that were stored in a space where airside economization was not used. In the 4 years of the modular data center's servers' operation, none of the servers failed. This observation highlights an opportunity to significantly save data center cooling energy by allowing IT equipment to operate outside the currently recommended and allowable ASHRAE envelopes and outside the ISA severity level G1.

Commentary by Dr. Valentin Fuster
J. Electron. Packag. 2017;139(2):021003-021003-11. doi:10.1115/1.4036356.

This paper describes the use of the double cantilever beam (DCB) method for characterizing the adhesion strength of interfaces in advanced microelectronic packages at room and high temperatures. Those interfaces include silicon–epoxy underfill, solder resist–epoxy underfill and epoxy mold compounds (EMCs), and die passivation materials–epoxy underfill materials. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon–underfill samples and cracking of solder resist films in solder resist–underfill samples. An asymmetric DCB configuration (i.e., different cantilever beam thickness on top compared to the bottom) was found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Furthermore, in order to characterize the adhesion strength of those interfaces at elevated temperatures seen during package assembly and end-user testing, an environmental chamber was designed and fabricated to rapidly and uniformly heat the DCB samples for testing at high temperatures. This chamber was used to successfully measure the adhesion strength of silicon–epoxy underfill samples at temperatures up to 260 °C, which is the typical maximum temperature experienced by electronic packages during solder reflow. For the epoxy underfills tested in this study, the DCB samples failed cohesively within the underfill at room temperature but started failing adhesively at temperatures near 150 °C. Adhesion strength measurements also showed a clear degradation with temperature. Several other case studies using DCB for material selection and assembly process optimization are also discussed. Finally, fractography results of the fractured surfaces are presented for better understanding of the failure mode.

Commentary by Dr. Valentin Fuster

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