Research Papers

Power and Thermal Constraints-Driven Modeling and Optimization for Through Silicon Via-Based Power Distribution Network

[+] Author and Article Information
Weijun Zhu, Yintang Yang

School of Microelectronics,
Xidian University,
Xi'an 710071, Shaanxi, China

Gang Dong

School of Microelectronics,
Xidian University,
Xi'an 710071, Shaanxi, China
e-mail: gdong@xidian.edu.cn

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received January 25, 2018; final manuscript received June 23, 2018; published online August 3, 2018. Assoc. Editor: Mehdi Asheghi.

J. Electron. Packag 140(4), 041002 (Aug 03, 2018) (10 pages) Paper No: EP-18-1007; doi: 10.1115/1.4040670 History: Received January 25, 2018; Revised June 23, 2018

The design of three-dimensional (3D) power delivery network (PDN) is constrained by both power and thermal integrity. Through-silicon via (TSV) as an important part of transmission power and heat in stack, the rational design of TSV layout is particularly important. Using minimal TSV area to achieve the required 3D PDN is significant to reduce manufacturing costs and increase integration. In this paper, we propose electrical and thermal models of 3D PDN, respectively, and we use them to solve the 3D voltage drop and temperature distribution problems. The accuracy and efficiency of our proposed methods are demonstrated by simulation measurement. Combining these two methods, a layer-based optimization solution is developed and allows us to adjust the TSV density for different layers while satisfying the global power and thermal constraints. This optimization is scalable and has the same guiding value for multichip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method.

Copyright © 2018 by ASME
Your Session has timed out. Please sign back in to continue.


Shen, W. , Lin, Y. , Chen, S. , Chang, H. , Chang, T. , Lo, W. , Li, C. , Chou, Y. , Kwai, D. , Kao, M. , and Chen, K. , 2018, “ 3D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV),” IEEE J. Electron Devices Soc., 6, pp. 396–402. [CrossRef]
Croes, K. , Messemaeker, J. D. , Li, Y. , Guo, W. , Pedreira, O. V. , Cherman, V. , Stucchi, M. , Wolf, I. D. , and Beyne, E. , 2016, “ Reliability Challenges Related to TSV Integration and 3D Stacking,” IEEE Des. Test, 33(3), pp. 37–45. [CrossRef]
Lau, J. H. , 2016, “ Recent Advances and New Trends in Flip Chip Technology,” ASME J. Electron. Packag., 138(3), p. 030802. [CrossRef]
Thadesar, P. A. , Gu, X. , Alapati, R. , and Bakir, M. S. , 2016, “ Through-Silicon Vias: Drivers, Performance, and Innovations,” IEEE Trans. Compon., Packag., Manuf. Technol., 6(7), pp. 1007–1017. [CrossRef]
Lee, H. M. , Liu, E. X. , Samudra, G. , Li, E. P. , Li, H. Y. , and Teo, K. H. , 2016, “ Power Integrity Modeling and Measurement of TSV-Based 3D IC System With Application to the Analysis of Seven-Chip Stack,” IEEE Electromagn. Compat. Mag., 5(3), pp. 52–60.
Kaddi, P. , Reddy, B. K. , and Singh, S. G. , 2014, “ Active Cooling Technique for Efficient Heat Mitigation in 3D-ICs,” 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, Mumbai, India, Jan. 5–9, pp. 495–498.
Hwang, J. S. , Seo, S. H. , and Lee, W. J. , 2016, “ Effect of Design Parameters on Thermomechanical Stress in Silicon of Through-Silicon Via,” ASME J. Electron. Packag., 138(3), p. 031006. [CrossRef]
Dong, G. , Shi, T. , Zhao, Y. B. , and Yang, Y. T. , 2015, “ An Analytical Model of Thermal Mechanical Stress Induced by Through Silicon Via,” Chin. Phys. B, 24(5), p. 056601. [CrossRef]
Tavakkoli, F. , Ebrahimi, S. , Wang, S. , and Vafai, K. , 2016, “ Thermophysical and Geometrical Effects on the Thermal Performance and Optimization of a Three-Dimensional Integrated Circuit,” ASME J. Heat Transfer, 138(8), p. 082101. [CrossRef]
ITRS Group, 2016, “ International Technology Roadmap for Semiconductors (ITRS),” ITRS Group Ltd., London, accessed Aug. 19, 2017, http://www.itrs2.net/
Plas, G. V. , Limaye, P. , Loi, I. , Mercha, A. , Oprins, H. , Torregiani, C. , Thijs, S. , Linten, D. , Stucchi, M. , Katti, G. , Velenis, D. , Cherman, V. , Vandevelde, B. , Simons, V. , Wolf, I. D. , Labie, R. , Perry, D. , Bronckers, S. , Minas, N. , Cupac, M. , Ruythooren, W. , Olmen, J. V. , Phommahaxay, A. , Broeck, M. , Opdebeeck, A. , Rakowski, M. , Wachter, B. D. , Dehan, M. , Nelis, M. , Agarwal, R. , Pullini, A. , Angiolini, F. , Benini, L. , Dehaene, W. , Travaly, Y. , Beyne, E. , and Marchal, P. , 2011, “ Design Issues and Considerations for Low-Cost 3D TSV IC Technology,” IEEE J. Solid-St Circ., 46(1), pp. 293–307. [CrossRef]
Swaminathan, M. , Kim, J. , Novak, I. , and Libous, J. P. , 2004, “ Power Distribution Networks for System-on-Package: Status and Challenges,” IEEE Trans. Adv. Packag., 27(2), pp. 286–300. [CrossRef]
Jin, J. , Zhao, W. , Wang, D. , Chen, H. , Li, E. , and Yin, W. , 2018, “ Investigation of Carbon Nanotube-Based Through-Silicon Vias for PDN Applications,” IEEE Trans. Electromagn. Compat., 60(3), pp. 738–746. [CrossRef]
Pak, J. S. , Kim, J. , Cho, J. , Kim, K. , Song, T. , Ahn, S. , Lee, J. , Lee, H. , Park, K. , and Kim, J. , 2011, “ PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models,” IEEE Trans. Compon., Packag., Manuf. Technol., 1(2), pp. 208–219. [CrossRef]
Kim, K. , Yook, J. M. , Kim, J. , Kim, H. , Lee, J. , Park, K. , and Kim, J. , 2013, “ Interposer Power Distribution Network (PDN) Modeling Using a Segmentation Method for 3D ICs With TSVs,” IEEE Trans. Compon., Packag., Manuf. Technol., 3(11), pp. 1891–1906. [CrossRef]
Kim, K. , Hwang, C. , Koo, K. , Cho, J. , Kim, H. , Kim, J. , Lee, J. , Lee, H. , Park, K. , and Pak, J. , 2012, “ Modeling and Analysis of a Power Distribution Network in TSV-Based 3D Memory IC Including P/G TSVs, on-Chip Decoupling Capacitors, and Silicon Substrate Effects,” IEEE Trans. Compon., Packag., Manuf. Technol., 2(12), pp. 2057–2070. [CrossRef]
Jain, A. , Jones, R. E. , Chatterjee, R. , and Pozder, S. , 2010, “ Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits,” IEEE Trans. Compon. Packag. Technol., 33(1), pp. 56–63. [CrossRef]
Oprins, H. , Cherman, V. , Stucchi, M. , Vandevelde, B. , Van der Plas, G. , Marchal, P. , and Beyne, E. , 2011, “ Steady State and Transient Thermal Analysis of Hot Spots in 3D Stacked ICs Using Dedicated Test Chips,” 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, San Jose, CA, Mar. 20–24, pp. 131–137.
Lee, Y.-J. , and Lim, S. K. , 2011, “ Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 30(11), pp. 1635–1648. [CrossRef]
Leila, C. , and Ankur, J. , 2015, “ An Explicit Analytical Model for Rapid Computation of Temperature Field in a Three-Dimensional Integrated Circuit (3D IC),” Int. J. Therm. Sci., 87, pp. 103–109. [CrossRef]
Haji-Sheikh, A. , and Beck, J. V. , 2002, “ Temperature Solution in Multi-Dimensional Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 45(9), pp. 1865–1877. [CrossRef]
Lu, T. and M., J. J. , 2014, “ Transient Electrical–Thermal Analysis of 3-D Power Distribution Network With FETI-Enabled Parallel Computing,” IEEE Trans. Compon., Packag., Manuf. Technol., 4(10), pp. 1684–1695. [CrossRef]
Ren, X. L. , Xu, C. , Ping, Y. , Wang, Z. , Pang, C. , and Yu, D. Q. , 2013, “ Electrical-Thermal Co-Simulation for Power Redistribution Layers of Interposer With Through-Silicon Vias,” 14th International Conference on Electronic Packaging Technology, Dalian, China, Aug. 11–14, pp. 492–497.
Yu, L. , Yang, H. G. , Jing, T. T. , Xu, M. , Geer, R. , and Wang, W. , 2010, “ Electrical Characterization of RF TSV for 3D Multi-Core and Heterogeneous ICs,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 7–11, pp. 686–693.
Kinoshita, T. , Kawakami, T. , Hori, T. , Matsumoto, K. , Kohara, S. , Orii, Y. , Yamada, F. , and Kada, M. , 2012, “ Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package,” ASME J. Electron. Packag., 134(2), p. 020903. [CrossRef]
Artur, C. , and Dawid, T. , 2014, Finite Volume Method in Heat Conduction, Springer, Dordrecht, The Netherlands, p. 68.
Xu, Z. , Wu, Q. , He, H. , and Lu, J. J. Q. , 2013, “ Electromagnetic-Simulation Program With Integrated Circuit Emphasis Modeling, Analysis, and Design of 3D Power Delivery,” IEEE Trans. Compon., Packag. Manuf. Technol., 3(4), pp. 641–652. [CrossRef]
Huang, G. , Bakir, M. , Naeemi, A. , Chen, H. , and Meindl, J. D. , 2007, “ Power Delivery for 3D Chips Stacks: Physical Modeling and Design Implications,” IEEE Electrical Performance of Electronic Packaging, Atlanta, GA, Oct. 29–31, pp. 205–208.
Bermond, C. , Cadix, L. , Farcy, A. , Lacrevaz, T. , Leduc, P. , and Flechet, B. , 2009, “ High Frequency Characterization and Modeling of High Density TSV in 3D Integrated Circuits,” IEEE Workshop on Signal Propagation on Interconnects, Strasbourg, France, May 12–15.
Intel Corporation, 2016, “ Intel Xeon Processor,” Intel Corporation, Santa Clara, CA, accessed Dec. 10, 2017, https://www.intel.com/content/www/us/en/products/processors/xeon/e7-processors.html
Ye, H. Q. , Wei, X. C. , and Li, E. P. , 2015, “ A Novel Semi-Analytical Solution of Impedance of Grid-Type Power Distribution Network,” IEEE International Symposium on Electromagnetic Compatibility (EMC), Dresden, Germany, Aug. 16–22, pp. 606–611.
Na, N. , and Swaminathan, M. , 1999, “ Modeling and Transient Simulation of Planes in Electronic Packages for GHz Systems,” IEEE Eighth Topical Meeting on Electrical Performance of Electronic Packaging, San Diego, CA, Oct. 25–27, pp. 149–152.
Kahng, A. B. , Li, B. , Peh, L. S. , and Samadi, K. , 2012, “ ORION 2.0: A Power-Area Simulator for Interconnection Networks,” IEEE Trans. Very Large Scale Integr. Syst., 20(1), pp. 191–196. [CrossRef]
Lu, B. , Hou, L. , Fu, J. , and Wang, J. , 2014, “ Simplified Empirical Formula on TSV Thermal Analysis for 3D IC EDA,” 12th IEEE International Conference on Solid State and Integrated Circuit Technology (ICSICT), Guilin, China, Oct. 28–31, pp. 1–3.
Wang, J. , Carson, J. K. , North, M. F. , and Cleland, D. J. , 2006, “ A New Approach to Modelling the Effective Thermal Conductivity of Heterogeneous Materials,” Int. J. Heat Mass Transfer, 49(17–18), pp. 3075–3083. [CrossRef]
Tian, W. , and Cui, H. , 2016, “ A Simplification Method of TSV Interposer for Thermal Analysis in 3D Packages,” 16th International Conference on Electronic Packaging Technology (ICEPT), Wuhan, China, Aug. 16–19, pp. 820–823.
Liu, Z. , Swarup, S. , Tan, S. X.-D. , Chen, H. B. , and Wang, H. , 2014, “ Compact Lateral Thermal Resistance Model of TSVs for Fast Finite Difference Based Thermal Analysis of 3D Stacked ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 33(10), pp. 1490–1502. [CrossRef]
Tavakkoli, F. , Ebrahimi, S. , Wang, S. , and Vafai, K. , 2016, “ Analysis of Critical Thermal Issues in 3D Integrated Circuits,” Int. J. Heat Mass Transfer, 97, pp. 337–352. [CrossRef]
Duffy, A. P. , Martin, A. J. , Orlandi, A. , Antonini, G. T. , Benson, M. , and Woolfson, M. S. , 2006, “ Feature Selective Validation (FSV) for Validation of Computational Electromagnetics (CEM)—Part I: the FSV Method,” IEEE Trans. Electromagn. Compat., 48(3), pp. 449–459. [CrossRef]
He, H. , and Lu, J. Q. , 2013, “ Compact Models of Voltage Drops in Power Delivery Network for TSV-Based Three-Dimensional Integration,” IEEE Electron Device Lett., 34(3), pp. 438–440. [CrossRef]
Xu, H. , Pavlidis, F. V. , and Micheli, D. G. , 2011, “ Analytical Heat Transfer Model for Thermal Through-Silicon Vias,” Design, Automation & Test in Europe (DATE), Grenoble, France, Mar. 14–18, pp. 1–6.
Leila, C. , Jared, J. , and Ankur, J. , 2017, “ Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits,” ASME J. Electron. Packag., 139(2), p. 020908. [CrossRef]
Oprins, H. , Cherman, V. , Vandevelde, B. , Torregiani, C. , Stucchi, M. , Van der Plas, G. , Marchal, P. , and Beyne, E. , 2011, “ Characterization of the Thermal Impact of Cu-Cu Bonds Achieved using TSVs on Hot Spot Dissipation in 3D Stacked ICs ,” IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 31–June 3, pp. 861–868.
Colgan, E. G. , Andry, P. , Dang, B. , Magerlein, J. H. , Maria, J. , Polastre, R. J. , and Wakil, J. , 2012, “ Measurement of Microbump Thermal Resistance in 3D Chip Stacks,” 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), San Jose, CA, Mar. 18–22, pp. 1–7.
Wei, H. , Wu, T. F. , Sekar, D. , Cronquist, B. , Pease, R. F. , and Mitra, S. , 2012, “ Cooling Three-Dimensional Integrated Circuits Using Power Delivery Networks,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 10–13, pp. 14.2.1–14.2.4.


Grahic Jump Location
Fig. 1

Schematic diagram of the 3D PDN in a chip stack

Grahic Jump Location
Fig. 2

View of the geometry of the grid-type PDN and the equivalent plane PDN

Grahic Jump Location
Fig. 3

The definition of multi-input equivalent impedance considering the influence of all the ports

Grahic Jump Location
Fig. 4

Schematic diagram of seven finite volume elements for FVM

Grahic Jump Location
Fig. 5

Impedance obtained by our proposed method and the full-wave simulation: (a) without decoupling capacitor and (b) with decoupling capacitor

Grahic Jump Location
Fig. 6

The normalized impedance with different TSV densities, the frequency up to 100 GHz: (a) without the impact of TSVs and (b) including the impact of TSVs

Grahic Jump Location
Fig. 7

The voltage drop with different frequencies and TSV densities: (a) power dissipation of 125 W and (b) power dissipation of 150 W

Grahic Jump Location
Fig. 8

(a) The equivalent normalized impedance of each chip including the cumulative effect of TSV and (b) voltage drops of different chip locations in a four-layer stacked chip

Grahic Jump Location
Fig. 9

Maximum temperature obtained by FEM simulation and our proposed model: (a) with power distribution of l-l-h-h and (b) with power distribution of h-h-l-l

Grahic Jump Location
Fig. 10

(a) Cross section temperature profile of the BEOL and ILD layer of the bottom chip and (b) side temperature profile of a four-layer chip stack

Grahic Jump Location
Fig. 11

Flowchart of the simultaneous electrical and thermal optimization method of 3D ICs



Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In