Power and thermal constraints-driven modeling and optimization for through silicon via-based power distribution network

[+] Author and Article Information
Weijun Zhu

School of Microelectronics, Xidian University, Xi'an, Shanxi, 710071, China

Gang Dong

School of Microelectronics, Xidian University, Xi'an, Shanxi, 710071, China

Yintang Yang

School of Microelectronics, Xidian University, Xi'an, Shanxi, 710071, China

1Corresponding author.

ASME doi:10.1115/1.4040670 History: Received January 25, 2018; Revised June 23, 2018


The design of 3-D power delivery network (3-D PDN) is constrained by both power and thermal integrity. Through-silicon via (TSV) as an important part of transmission power and heat in stack, the rational design of TSV layout is particularly important. Using minimal TSV area to achieve the required PDN reduces manufacturing costs and increases integration. In this paper, we propose electrical and thermal models of 3-D PDNs, respectively, and we use them to solve the three-dimensional voltage drop and temperature distribution problems. The accuracy and efficiency of our proposed methods are demonstrated by simulation measurement. Combining these two methods, a layer-based optimization solution is developed and allows us to adjust the TSV density for different layers while satisfying the global power and thermal constraints. This optimization is scalable and has the same guiding value for multi-chip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method.

Copyright (c) 2018 by ASME
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