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Research Papers

Power and Thermal Constraints-Driven Modeling and Optimization for Through Silicon Via-Based Power Distribution Network

[+] Author and Article Information
Weijun Zhu, Yintang Yang

School of Microelectronics,
Xidian University,
Xi'an 710071, Shaanxi, China

Gang Dong

School of Microelectronics,
Xidian University,
Xi'an 710071, Shaanxi, China
e-mail: gdong@xidian.edu.cn

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received January 25, 2018; final manuscript received June 23, 2018; published online August 3, 2018. Assoc. Editor: Mehdi Asheghi.

J. Electron. Packag 140(4), 041002 (Aug 03, 2018) (10 pages) Paper No: EP-18-1007; doi: 10.1115/1.4040670 History: Received January 25, 2018; Revised June 23, 2018

The design of three-dimensional (3D) power delivery network (PDN) is constrained by both power and thermal integrity. Through-silicon via (TSV) as an important part of transmission power and heat in stack, the rational design of TSV layout is particularly important. Using minimal TSV area to achieve the required 3D PDN is significant to reduce manufacturing costs and increase integration. In this paper, we propose electrical and thermal models of 3D PDN, respectively, and we use them to solve the 3D voltage drop and temperature distribution problems. The accuracy and efficiency of our proposed methods are demonstrated by simulation measurement. Combining these two methods, a layer-based optimization solution is developed and allows us to adjust the TSV density for different layers while satisfying the global power and thermal constraints. This optimization is scalable and has the same guiding value for multichip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method.

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Figures

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Fig. 1

Schematic diagram of the 3D PDN in a chip stack

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Fig. 2

View of the geometry of the grid-type PDN and the equivalent plane PDN

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Fig. 3

The definition of multi-input equivalent impedance considering the influence of all the ports

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Fig. 4

Schematic diagram of seven finite volume elements for FVM

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Fig. 5

Impedance obtained by our proposed method and the full-wave simulation: (a) without decoupling capacitor and (b) with decoupling capacitor

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Fig. 6

The normalized impedance with different TSV densities, the frequency up to 100 GHz: (a) without the impact of TSVs and (b) including the impact of TSVs

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Fig. 7

The voltage drop with different frequencies and TSV densities: (a) power dissipation of 125 W and (b) power dissipation of 150 W

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Fig. 8

(a) The equivalent normalized impedance of each chip including the cumulative effect of TSV and (b) voltage drops of different chip locations in a four-layer stacked chip

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Fig. 9

Maximum temperature obtained by FEM simulation and our proposed model: (a) with power distribution of l-l-h-h and (b) with power distribution of h-h-l-l

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Fig. 10

(a) Cross section temperature profile of the BEOL and ILD layer of the bottom chip and (b) side temperature profile of a four-layer chip stack

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Fig. 11

Flowchart of the simultaneous electrical and thermal optimization method of 3D ICs

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