0
Research Papers

Edge Trimming Induced Defects on Direct Bonded Wafers

[+] Author and Article Information
Fumihiro Inoue

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Fumihiro.Inoue@imec.be

Anne Jourdain

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Anne.Jourdain@imec.be

Lan Peng

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Lan.Peng@imec.be

Alain Phommahaxay

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Alain.Phommahaxay@imec.be

Daisuke Kosemura

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Daisuke.Kosemura@imec.be

Ingrid De Wolf

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium;
Department of Materials Engineering,
KU Leuven,
Kasteelpark Arenberg 44,
Leuven 3001, Belgium
e-mail: Ingrid.DeWolf@imec.be

Kenneth June Rebibis

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Kenneth.June.Rebibis@imec.be

Andy Miller

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Andy.Miller@imec.be

Erik Sleeckx

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Erik.Sleeckx@imec.be

Eric Beyne

IMEC,
Kapeldreef 75,
Leuven 3001, Belgium
e-mail: Eric.Beyne@imec.be

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 11, 2017; final manuscript received February 14, 2018; published online May 11, 2018. Assoc. Editor: Yi-Shao Lai.

J. Electron. Packag 140(3), 031004 (May 11, 2018) (6 pages) Paper No: EP-17-1127; doi: 10.1115/1.4040002 History: Received December 11, 2017; Revised February 14, 2018

The diamond abrasive process which is applied onto the silicon wafer edge, the so called “edge trimming,” is an important step in three-dimensional microelectronics processing technology, due to the significant thickness reduction of the wafer after thinning. Nevertheless, the wafer edge defects caused by edge trimming have often been overlooked. Although the mechanisms of the formation of the defects in Si due to trimming may be similar to the ones caused by grinding, an in-depth study and risk assessment have not been done yet. In addition, the variety of stress relief processing options can give different morphology and defect removal behavior on the edge trimmed Si sidewall. In a first study, we used transmission electron microscopy and Raman spectroscopy to analyze the defects caused by edge trimming. We show the presence of a continuous layer of amorphous Si and of different phases of Si, caused by edge trimming. A comparison of the damage induced in the Si by two different integration schemes is also discussed. When polishing is used for stress release, the observed sidewall defects stay, since the polishing force is only applied on the top surface of the wafer. On the other hand, the damage is completely removed for the case of wet and dry etching. The surface chemical reactions occurring at the surface during these processes are also acting on the Si sidewall. These findings provide a workable edge trimming and stress relief method for permanently bonded wafers, with many industrial applications.

FIGURES IN THIS ARTICLE
<>
Copyright © 2018 by ASME
Your Session has timed out. Please sign back in to continue.

References

Kagawa, Y. , Fujii, N. , Aoyagi, K. , Kobayashi, Y. , Nishi, S. , Todaka, N. , Takeshita, S. , Taura, J. , Takahashi, H. , Nishimura, K. , Tatani, M. , Kawamura, M. , Nakayama, H. , Nagano, T. , Ohno, K. , Iwamoto, H. , Kadomura, S. , and Hirayama, T. , 2016, “ Novel Stacked CMOS Image Sensor With Advanced Cu2Cu Hybrid Bonding,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 3–7, pp. 8.4.1–8.4.4.
Schmidt, M. A. , 1998, “ Wafer-to-Wafer Bonding for Microstructure Formation,” Proc. IEEE, 86(8), pp. 1575–1585. [CrossRef]
Kim, S.-W. , Detalle, M. , Peng, L. , Nolmans, P. , Heylen, N. , Velenis, D. , Miller, A. , Beyer, G. , and Beyne, E. , 2016, “ Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined With a Via-Middle Through-Silicon-Via Process,” IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 31–June 3, p. 1180.
Wang, C. , and Suga, T. , 2011, “ Room-Temperature Direct Bonding Using Fluorine Containing Plasma Activation,” J. Electrochem. Soc., 158(5), pp. H525–H529. [CrossRef]
Inoue, F. , Jourdain, A. , Peng, L. , Phommahaxay, A. , De Vos, J. , June Rebibis, K. , Miller, A. , Sleeckx, E. , Beyne, E. , and Uedono, A. , 2017, “ Influence of Si Wafer Thinning Processes on (Sub)Surface Defects,” Appl. Surf. Sci., 404, pp. 82–87. [CrossRef]
Pei, Z. J. , Fisher, G. R. , and Liu, J. , 2008, “ Grinding of Silicon Wafers: A Review From Historical Perspectives,” Int. J. Mach. Tools Manuf., 48(12–13), pp. 1297–1307. [CrossRef]
Mizushima, Y. , Kim, Y. , Nakamura, T. , Sugie, R. , Hashimoto, H. , Uedono, A. , and Ohba, T. , 2014, “ Impact of Back-Grinding-Induced Damage on Si Wafer Thinning for Three-Dimensional Integration,” Jpn. J. Appl. Phys., 53(5S2), p. 05GE04. [CrossRef]
Mizushima, Y. , Kim, Y. , Nakamura, T. , Uedono, A. , and Ohba, T. , 2017, “ Behavior of Copper Contamination on Backside Damage for Ultra-Thin Silicon Three Dimensional Stacking Structure,” Microelectron. Eng., 167, pp. 23–31. [CrossRef]
Kim, Y.-S. , Maeda, N. , Kitada, H. , Fujimoto, K. , Kodama, S. , Kawai, A. , Arai, K. , Suzuki, K. , Nakamura, T. , and Ohba, T. , 2013, “ Advanced Wafer Thinning Technology and Feasibility Test for 3D Integration,” Microelectron. Eng., 107, pp. 65–71. [CrossRef]
Pei, Z. J. , and Strasbaugh, A. , 2001, “ Fine Grinding of Silicon Wafers,” Int. J. Mach. Tools Manuf., 41(5), pp. 659–672. [CrossRef]
Pei, Z. J. , 2002, “ A Study on Surface Grinding of 300 mm Silicon Wafers,” Int. J. Mach. Tools Manuf., 42(3), pp. 385–393. [CrossRef]
Pei, Z. J. , Billingsley, S. R. , and Miura, S. , 1999, “ Grinding Induced Subsurface Cracks in Silicon Wafers,” Int. J. Mach. Tools Manuf., 39(7), pp. 1103–1116. [CrossRef]
Zhou, L. , Tian, Y. B. , Huang, H. , Sato, H. , and Shimizu, J. , 2012, “ A Study on the Diamond Grinding of Ultra-Thin Silicon Wafers,” Proc. Inst. Mech. Eng., Part B, 226(1), p. 66. [CrossRef]
Zarudi, I. , and Zhang, L. C. , 1998, “ Effect of Ultraprecision Grinding on the Microstructural Change in Silicon Monocrystals,” J. Mater. Process. Technol., 84(1–3), pp. 149–158. [CrossRef]
Ren, Q. , Wei, X. , Xie, X. , and Hu, W. , 2017, “ Simulation Research on Micro Contact Based on Force in Silicon Wafer Rotation Grinding,” Mater. Sci. Eng., 250, p. 012016.
Yang, Y. , De Munck, K. , Cotrin Teixeira, R. , Swinnen, B. , Verlinden, B. , and De Wolf, I. , 2008, “ Process Induced Sub-Surface Damage in Mechanically Ground Silicon Wafers,” Semicond. Sci. Technol., 23(7), p. 075038. [CrossRef]
Gao, S. , Kang, R. , Dong, Z. , and Zhang, B. , 2013, “ Edge Chipping of Silicon Wafers in Diamond Grinding,” Int. J. Mach. Tools Manuf., 64, pp. 31–37. [CrossRef]
Inoue, F. , Jourdain, A. , Visker, J. , Peng, L. , Moeller, B. , Yokoyama, K. , Phommahaxay, A. , June Rebibis, K. , Miller, A. , Beyne, E. , and Sleeckx, E. , 2017, “ Edge Trimming for Surface Activated Dielectric Bonded Wafers,” Microelectron. Eng., 167, pp. 10–16. [CrossRef]
Lei, W.-S. , Kumar, A. , and Yalamanchili, R. , 2012, “ Die Singulation Technologies for Advanced Packaging: A Critical Review,” J. Vac. Sci. Technol., B, 30(4), p. 040801. [CrossRef]
Kim, S.-W. , Peng, L. , Miller, A. , Beyer, G. , Beyne, E. , and Lee, C.-S. , 2015, “ Permanent Wafer Bonding in the Low Temperature by Using Various Plasma Enhanced Chemical Vapour Deposition Dielectrics,” 3D Systems Integration Conference (3DIC), Sendai, Japan, Aug. 31–Sept. 2, pp. TS7.2.1–TS7.2.4.
Peng, L. , Kim, S.-W. , Inoue, F. , Wang, T. , Phommahaxay, A. , Verdonck, P. , Jourdain, A. , Vos, J. D. , Sleeckx, E. , Struyf, H. , Miller, A. , Beyer, G. , and Beyne, E. , 2016, “ Development of Multi-Stack Dielectric Wafer Bonding,” 17th International Conference on Electronic Packaging Technology (ICEPT), Wuhan, China, Aug. 16–19, p. 22.
Inoue, F. , Peng, L. , Phommahaxay, A. , Kim, S.-W. , Vos, J. D. , Sleeckx, E. , Miller, A. , Beyer, G. , and Beyne, E. , 2017, “ Characterization of Inorganic Dielectric Layers for Low Thermal Budget Wafer-to-Wafer Bonding,” Fifth Low Temperature Bonding for 3D Integration (LTB-3D), Tokyo, Japan, May 16–18, p. 24.
Jang, J. I. , Lance, M. J. , Wen, S. , Tsui, T. Y. , and Pharr, G. M. , 2005, “ Indentation-Induced Phase Transformations in Silicon: Influences of Load, Rate and Indenter Angle on the Transformation Behavior,” Acta Mater., 53(6), pp. 1759–1770. [CrossRef]
Das, C. R. , Hsu, H. C. , Dhara, S. , Bhaduri, A. K. , Raj, B. , Chen, L. C. , Chen, K. H. , Albert, S. K. , Ray, A. , and Tzeng, Y. , 2009, “ A Complete Raman Mapping of Phase Transitions in Si Under Indentation,” J. Raman Spectrosc., 41, p. 3.
Kailer, A. , Gogotsi, Y. G. , and Nickel, K. G. , 1997, “ Phase Transformations of Silicon Caused by Contact Loading,” J. Appl. Phys., 81(7), p. 3057.
Raj Marks, M. , Hassan, Z. , and Cheong, K.-Y. , 2014, “ Cu Retardation Performance of Extrinsic Gettering Layers in Thinned Wafers Evaluated by Transient Capacitance Measurement,” IEEE Trans. Compon. Packag. Manuf. Technol., 4(12), p. 12.
Ogawa, H. , Yanagisawa, M. , Kikuchi, J. , and Horiike, Y. , 2003, “ Study on the Mechanism of Silicon Chemical Mechanical Polishing Employing In Situ Infrared Spectroscopy,” Jpn. J. Appl. Phys., 42(Pt 1, 2A), p. 587. [CrossRef]
Watanabe, N. , Miyazaki, T. , Yoshikawa, K. , and Aoyagi, M. , 2014, “ Damage Evaluation of Wet-Chemical Si-Wafer Thinning/Backside Via Exposure Process,” IEEE Trans. Compon. Packag. Manuf. Technol., 4(4), pp. 741–747.
Michaud, P. T. , and Babic, D. , 1998, “ A Raman Study of Etching Silicon in Aqueous Tetramethylammonium Hydroxide,” J. Electrochem. Soc., 145(11), pp. 4040–4043.
Draney, N. R. , Liu, J. J. , and Jiang, T. , 2004, “ Experimental Investigation of Bare Silicon Wafer Warp,” IEEE Workshop on Microelectronics and Electron Devices, Boise, ID, Apr. 16, pp. 120–123.
Jiun, H. H. , Ahmad, I. , Jalar, A. , and Omar, G. , 2006, “ Effect of Wafer Thinning Methods Towards Fracture Strength and Topography of Silicon Die,” Microelectron. Reliab., 46(5–6), pp. 836–845. [CrossRef]

Figures

Grahic Jump Location
Fig. 1

Schematic drawing of direct bonded wafer after grinding: (a) edge trimming before bonding and (b) edge trimming after bonding

Grahic Jump Location
Fig. 7

Raman spectra of the edge trimmed Si sidewall of the top wafer on direct bonded wafer after different stress relief processing. The 15 points were measured at around middle toward the depth direction. (a) CMP, (b) wet etch, and (c) dry etch.

Grahic Jump Location
Fig. 6

Cross-sectional TEM images of edge trimmed Si sidewall on direct bonded wafer after grinding and different stress relief processing. The edge trimming is applied after bonding. (a) At extreme edge with CMP surface and (b) its high magnification. (c) At extreme edge with wet etched surface and (d) its high magnification. (e) At extreme edge with dry etched surface and (f) its high magnification.

Grahic Jump Location
Fig. 5

Lateral view of SEM images of edge trimmed Si sidewall on direct bonded wafer after grinding and stress relief processing. The edge trimming process was applied after bonding. (a) CMP, (b) wet etch, and (c) dry etch.

Grahic Jump Location
Fig. 4

Cross-sectional TEM images of edge trimmed Si sidewall on direct bonded wafer after grinding. Edge trimming before grinding: (a) at extreme edge with grinding surface and (b) high magnification on a defect. Edge trimming after bonding: (c) at extreme edge with grinding surface and (d) high magnification on a defect.

Grahic Jump Location
Fig. 3

Raman spectra of the edge trimmed Si sidewall of the top wafer on direct bonded wafer. The line scans with 15 points were measured at around the middle of the edge trimmed sidewall. (a) Edge trimming before bonding and (b) edge trimming after bonding.

Grahic Jump Location
Fig. 2

SEM image of the direct bonded wafer at edge: (a) bird's view, (b) lateral view from bevel, and (c) high magnification lateral view on edge trimmed side wall for edge trim before bonding. The chipping indicated in (c) is created edge trimming before bonding. Same for edge trimming after bonding: (d) bird's view and (e) lateral view from bevel.

Tables

Errata

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In