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Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

[+] Author and Article Information
Leila Choobineh

Mem. ASME
Mechanical Engineering,
SUNY Polytechnic Institute,
100 Seymour Road,
Utica, NY 13502
e-mail: Leila.choobineh@sunyit.edu

Jared Jones

Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019

Ankur Jain

Mem. ASME
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
e-mail: jaina@uta.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 16, 2016; final manuscript received March 27, 2017; published online June 12, 2017. Assoc. Editor: Justin A. Weibel.

J. Electron. Packag 139(2), 020908 (Jun 12, 2017) (6 pages) Paper No: EP-16-1140; doi: 10.1115/1.4036404 History: Received December 16, 2016; Revised March 27, 2017

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

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References

Banerjee, K. , Souri, S. J. , and Saraswat, K. C. , 2001, “ 3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration,” Proc. IEEE, 89(5), pp. 602–633. [CrossRef]
Patti, R. , 2006, “ Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs,” Proc. IEEE, 94(6), pp. 1214–1224. [CrossRef]
Beyne, E. , 2006, “ 3D System Integration Technologies,” International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA-Tech), Hsinchu, Taiwan, Apr. 24–26, pp. 1–9.
Said, F. , Abbott, D. , and Franzon, P. D. , 1998, “ A Review of 3-D Packaging Technology,” IEEE Trans. Compon. Packag. Manuf. Technol. Part B, 21(1), pp. 2–14. [CrossRef]
Knickerbocker, J. U. , Andry, P. S. , Dang, B. , Horton, R. R. , Patel, C. S. , Polastre, R. J. , Sakuma, K. , Sprogis, E. S. , Tsang, C. K. , Webb, B. C. , and Wright, S. L. , 2008, “ 3D Silicon Integration,” 58th Electronic Components and Technology Conference (ECTC), Orlando, FL, May 27–30, pp. 538–543.
Chan, V. W. C. , Chan, P. C. H. , and Chan, M. , 2001, “ Three-Dimensional CMOS SOI Integrated Circuit Using High Temperature Metal-Induced Lateral Crystallization,” IEEE Trans. Electron Devices, 48(7), pp. 1394–1399. [CrossRef]
Topol, A. W. , La Tulipe, D. C. , Shi, L. , Frank, D. J. , Bernstein, K. , Steen, S. E. , Kumar, A. , Singco, G. U. , Young, A. M. , Guarini, K. W. , and Leong, M. , 2006, “ Three-Dimensional Integrated Circuits,” IBM J. Res. Dev., 50(4/5), pp. 491–506.
Guarini, K. W. , Topol, A. T. , Leong, M. , Yu, R. , Shi, L. , Newport, M. R. , Frank, D. J. , Singh, D. V. , Cohen, G. M. , Nitta, S. V. , Boyd, D. C. , O'Neil, P. A. , Tempest, S. L. , Pogge, H. B. , Purushothaman, S. , and Haensch, W. E. , 2002, “ Electrical Integrity of State-of-the-Art 0.13l m SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA, Dec. 8–11, p. 943.
Brunschwiler, T. , Michel, B. , Rothuizen, H. , Kloter, U. , Wunderle, B. , Oppermann, H. , and Reichl, H. , 2009, “ Interlayer Cooling Potential in Vertically Integrated Packages,” Microsyst. Technol., 15(1), pp. 57–74. [CrossRef]
Schindler-Saefkow, F. , Wittler, O. , May, D. , and Michel, B. , 2006, “ Thermal Management in a 3D-PCB-Package With Water Cooling,” Electronics Systemintegration Technology Conference (ESTC), Dresden, Germany, Sept. 5–7, pp. 107–110.
Sikka, K. , Wakil, J. , Toy, H. , and Liu, H. , 2012, “ An Efficient Lid Design for Cooling Stacked Flip-Chip 3D Packages,” 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), San Diego, CA, May 30–June 1, pp. 606–611.
Cong, J. , Luo, G. , Wei, J. , and Zhang, Y. , 2007, “ Thermal-Aware 3D IC Placement Via Transformation,” Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 23–26, pp. 780–785.
Goplen, B. , and Sapatnekar, S. S. , 2006, “ Placement of Thermal Vias in 3D ICs Using Various Thermal Objectives,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26(4), pp. 692–709. [CrossRef]
Savidis, I. , Alam, S. , Jain, A. , Pozder, S. , Jones, R. E. , and Chatterjee, R. , 2010, “ Electrical Modeling and Characterization of Through-Silicon Vias (TSVs) for 3D Integrated Circuits,” Microelectron. J., 41(1), pp. 9–16. [CrossRef]
Pi, Y. , Wang, W. , and Jin, Y. , 2016, “ An Accurate Calculation Method on Thermal Effectiveness of TSV and Wire,” IEEE 18th Electronics Packaging Technology Conference (EPTC), Singapore, Nov. 30–Dec. 3, pp. 569–573.
Rencz, M. , 2005, “ Thermal Issues in Stacked Die Packages,” 21st Annual IEEE Semiconductor Thermal Measurement and Management Symposium (STHERM), San Jose, CA, Mar. 15–17, pp. 307–312.
Link, G. M. , and Vijaykrishnan, N. , 2006, “ Thermal Trends in Emerging Technologies,” 7th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, Mar. 27–29, pp. 625–632.
Loi, G. L. , Agrawal, B. , Srivastava, N. , Lin, S.-C. , Sherwood, T. , and Banerjee, K. , 2006, “ A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy,” 43rd ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 24–28, pp. 991–996.
Das, S. , Chandrakasan, A. , and Reif, R. , 2004, “ Timing, Energy, and Thermal Performance of Three Dimensional Integrated Circuits,” 14th ACM Great Lakes Symposium on VLSI, Boston, MA, Apr. 26–28, pp. 338–343.
Yan, H. , Zhou, Q. , and Hong, X. , 2009, “ Thermal Aware Placement in 3D ICs Using Quadratic Uniformity Modeling Approach,” Integr. VLSI J., 42(2), pp. 175–180. [CrossRef]
Kleiner, M. B. , Kuhn, S. A. , Ramm, P. , and Weber, W. , 1995, “ Thermal Analysis of Vertically Integrated Circuits,” International Electron Devices Meeting (IEDM) Technical Digest, Libertyville, IL, Dec. 10–13, pp. 487–490.
Chiang, T.-Y. , Souri, S. J. , Chui, C. O. , and Saraswat, K. C. , 2001, “ Thermal Analysis of Heterogeneous 3-D ICs With Various Integration Scenarios,” International Electron Devices Meeting (IEDM) Technical Digest, Washington, DC, Dec. 2–5, pp. 31.2.1–31.2.4.
Haji-Sheikh, A. , and Beck, J. V. , 2002, “ Temperature Solution in Multi-Dimensional Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 45(9) pp. 1865–1877. [CrossRef]
Cong, J. , Wei, J. , and Zhang, Y. , 2004, “ A Thermal-Driven Floorplanning Algorithm for 3D ICs,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 7–11, pp. 306–313.
Geer, J. , Desai, J. , and Sammakia, B. , 2007, “ Heat Conduction in Multilayered Rectangular Domains,” ASME J. Electron. Packag., 129(4), pp. 440–451 [CrossRef]
Ayala, J. L. , Sridhar, A. , and Cuesta, D. , 2010, “ Thermal Modeling and Analysis of 3D Multi-Processor Chips,” Integr. VLSI J., 43(4), pp. 327–341. [CrossRef]
Choobineh, L. , and Jain, A. , 2012, “ Analytical Solution for Steady-State and Transient Temperature Field in Vertically Integrated Three-Dimensional Integrated Circuits (3D ICs),” IEEE Trans. Compon. Packag. Manuf. Technol., 2(12), pp. 2031–2039. [CrossRef]
Choobineh, L. , and Jain, A. , 2013, “ Determination of Temperature Distribution in Three-Dimensional Integrated Circuits (3D ICs) With Unequally-Sized Die,” Appl. Therm. Eng., 56(1), pp. 176–184. [CrossRef]
Choobineh, L. , and Jain, A. , 2015, “ An Explicit Analytical Model for Rapid Computation of Temperature Field in a Three-Dimensional Integrated Circuit (3D IC),” Int. J. Therm. Sci., 87, pp. 103–109. [CrossRef]
Dogruoz, M. B. , 2016, “ Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations,” ASME J. Electron. Packag., 138(2), p. 021004. [CrossRef]
Wang, N. , Jin, Y. , Pi, Y. , and Wang, W. , 2016, “ A Full Chip Scale Numerical Simulation Method for Thermal Management of 3D IC,” 17th International Conference on Electronic Packaging Technology (ICEPT), Wuhan, China, Aug. 16–19, pp. 690–693.
Tavakkoli, F. , Ebrahimi, S. , Wang, S. , and Vafai, K. , 2016, “ Thermophysical and Geometrical Effects on the Thermal Performance and Optimization of a Three-Dimensional Integrated Circuit,” ASME J. Heat Transfer, 138(8), p. 082101. [CrossRef]
Jain, A. , Jones, R. E. , Chatterjee, R. , and Pozder, S. , 2010, “ Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits,” IEEE Trans. Compon. Packag. Technol., 33(1), pp. 56–63. [CrossRef]
Haji-Sheikh, A. , Beck, J. V. , and Agonafer, D. , 2003, “ Steady-State Heat Conduction in Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 46(13), pp. 2363–2379. [CrossRef]
Rahman, A. , and Reif, R. , 2001, “ Thermal Analysis of Three-Dimensional (3-D) Integrated Circuits (ICs),” IEEE International Interconnect Technology Conference (IITC), Burlingame, CA, June 4–6, pp. 157–159.
Oprins, H. , Cherman, V. O. , Vandevelde, B. , Van der Plas, G. , Marchal, P. , and Beyne, E. , 2012, “ Numerical and Experimental Characterization of the Thermal Behavior of a Packaged DRAM-on-Logic Stack,” IEEE 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29–June 1, pp. 1081–1088.
Li, J.-F. , and Wu, C.-W. , 2010, “ Is 3D Integration an Opportunity or Just a Hype?,” 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, Jan. 18–21, pp. 541–543.
Puttaswamy, K. , and Loh, G. H. , 2006, “ Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor,” 16th ACM Great Lakes Symposium on VLSI (GLSVLSI), Philadelphia, PA, Apr. 30–May 1, pp. 19–24.
Oprins, H. , Cherman, V. , Vandevelde, B. , Torregiani, C. , Stucchi, M. , Van derPlas, G. , Marchal, P. , and Beyne, E. , 2011, “ Characterization of the Thermal Impact of Cu-Cu Bonds Achieved Using TSVs on Hot Spot Dissipation in 3D Stacked ICs,” Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 31–June 3, pp. 861–868.
Colgan, E. G. , Andry, P. , Dang, B. , Magerlein, J. H. , Maria, J. , Polastre, R. J. , and Wakil, J. , 2012, “ Measurement of Microbump Thermal Resistance in 3D Chip Stacks,” 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), San Jose, CA, Mar. 18–22, pp. 1–7.
Choobineh, L. , Vo, N. , Uehling, T. , and Jain, A. , 2013, “ Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC),” ASME Paper No. IPACK2013-73167.
Matsumoto, K. , Ibaraki, S. , Sueoka, K. , Sakuma, K. , Kikuchi, H. , Orii, Y. , and Yamada, F. , 2011, “ Experimental Thermal Resistance Evaluation of a Three-Dimensional (3D) Chip Stack,” 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), San Jose, CA, Mar. 20–24, pp. 125–130.
Bozorg-Grayeli, E. , Reifenberg, J. P. , Asheghi, M. , Wong, H. S. P. , and Goodson, K. E. , 2013, “ Thermal Transport in Phase Change Memory Materials,” Annu. Rev. Heat Transfer., 16(1), pp. 397–428. [CrossRef]
Yovanovich, M. , 2005, “ Four Decades of Research on Thermal Contact, Gap, and Joint Resistance in Microelectronics,” IEEE Trans. Compon. Packag. Technol., 28(2), pp. 182–206. [CrossRef]
Joiner, B. , Montes de Oca, J. A. , and Neelakantan, S. , 2009, “ Measurement and Simulation of Stacked Die Thermal Resistances,” IEEE Trans. Compon. Packag. Technol., 32(4), pp. 709–715.
Hahn, D. W. , and Özisik, M. N. , 2012, Heat Conduction, 3rd ed., Wiley, Hoboken, NJ. [PubMed] [PubMed]

Figures

Grahic Jump Location
Fig. 1

Schematic of the two dies in the 3D IC. Blue lines show the heater, red lines show the top die sensor, and green lines show the bottom die sensor (see color figure online).

Grahic Jump Location
Fig. 2

The substrate mounted in the socket and soldered wires

Grahic Jump Location
Fig. 3

(a) Temperature rise in bottom die sensor versus time in the two-die stack for different amounts of thermal resistance between the two dies and (b) steady-state temperature rise in BDS for different amounts of thermal resistance between the two dies by applying 100 mA current (0.6 W power) in top die heater

Grahic Jump Location
Fig. 4

Thermal calibration curve for top and bottom die sensors

Grahic Jump Location
Fig. 5

The temperature rise in the bottom die sensor versus time by heating the top die for different values of coefficient of convective heat transfer: (a) finite element simulation and (b) experimental data

Grahic Jump Location
Fig. 6

Experimental setup for measuring the interdie thermal resistance between the two dies

Grahic Jump Location
Fig. 7

(a) Measured temperature rise in bottom die sensor (BDS) due to 100 mA current (0.6 W power) in top die heater (TDH) and (b) measured temperature rise in top die sensor (TDS) due to 80 mA current (0.37 W power) in bottom die heater (BDH)

Grahic Jump Location
Fig. 8

The geometry of copper pillars used to make attachment between the two dies

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