3D integrated circuits (ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement, reducing interconnect delay, and reducing manufacturing cost. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling in 3D ICs is important for improving thermal and electrical performance. A number of numerical and analytical models have been developed for thermal analysis of 3D ICs and several experimental investigations on the thermal measurement of 3D ICs have been done. However, there is a relative lack of experimental work to determine key physical parameters in 3D ICs thermal design. One such important parameter in thermal analysis is the inter-die thermal resistance between adjacent die bonded together. This paper describes a novel experimental method to measure the value of inter-die thermal resistance between two die in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the inter-die thermal resistance between the two die is determined. There is good agreement between experimental measurements and theoretically estimated value of the inter-die thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.