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Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

[+] Author and Article Information
Leila Choobineh

Mem. ASME
Mechanical Engineering,
SUNY Polytechnic Institute,
100 Seymour Road,
Utica, NY 13502
e-mail: Leila.choobineh@sunyit.edu

Jared Jones

Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019

Ankur Jain

Mem. ASME
Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
e-mail: jaina@uta.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 16, 2016; final manuscript received March 27, 2017; published online June 12, 2017. Assoc. Editor: Justin A. Weibel.

J. Electron. Packag 139(2), 020908 (Jun 12, 2017) (6 pages) Paper No: EP-16-1140; doi: 10.1115/1.4036404 History: Received December 16, 2016; Revised March 27, 2017

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

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Figures

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Fig. 1

Schematic of the two dies in the 3D IC. Blue lines show the heater, red lines show the top die sensor, and green lines show the bottom die sensor (see color figure online).

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Fig. 2

The substrate mounted in the socket and soldered wires

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Fig. 3

(a) Temperature rise in bottom die sensor versus time in the two-die stack for different amounts of thermal resistance between the two dies and (b) steady-state temperature rise in BDS for different amounts of thermal resistance between the two dies by applying 100 mA current (0.6 W power) in top die heater

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Fig. 4

Thermal calibration curve for top and bottom die sensors

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Fig. 5

The temperature rise in the bottom die sensor versus time by heating the top die for different values of coefficient of convective heat transfer: (a) finite element simulation and (b) experimental data

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Fig. 6

Experimental setup for measuring the interdie thermal resistance between the two dies

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Fig. 7

(a) Measured temperature rise in bottom die sensor (BDS) due to 100 mA current (0.6 W power) in top die heater (TDH) and (b) measured temperature rise in top die sensor (TDS) due to 80 mA current (0.37 W power) in bottom die heater (BDH)

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Fig. 8

The geometry of copper pillars used to make attachment between the two dies

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