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SPECIAL SECTION PAPERS

Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction

[+] Author and Article Information
Valeriy Sukharev

Mem. ASME
Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538
e-mail: valeriy_sukharev@mentor.com

Jun-Ho Choy

Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538
e-mail: junho_choy@mentor.com

Armen Kteyan

Mentor Graphics Corporation,
16 Halabyan Street,
Yerevan 0038, Armenia
e-mail: armen_kteyan@mentor.com

Henrik Hovsepyan

Mentor Graphics Corporation,
16 Halabyan Street,
Yerevan 0038, Armenia
e-mail: henrik_hovsepyan@mentor.com

Mark Nakamoto

Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: nakamoto@qti.qualcomm.com

Wei Zhao

Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: weizhao@qti.qualcomm.com

Riko Radojcic

Consultant
850 Beech Street, #610,
San Diego, CA 92101
e-mail: rradojcic@yahoo.com

Uwe Muehle

Department of Microelectronic
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: uwe.muehle@ikts-extern.fraunhofer.de

Ehrenfried Zschech

Department of Microelectronic
Materials and Nanoanalysis,
Fraunhofer Institute for Ceramic
Technologies and Systems IKTS,
Maria-Reiche-Strasse 2,
Dresden D-01109, Germany
e-mail: ehrenfried.zschech@ikts.fraunhofer.de

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 14, 2016; final manuscript received March 30, 2017; published online June 12, 2017. Assoc. Editor: S. Ravi Annapragada.

J. Electron. Packag 139(2), 020906 (Jun 12, 2017) (12 pages) Paper No: EP-16-1138; doi: 10.1115/1.4036402 History: Received December 14, 2016; Revised March 30, 2017

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.

Copyright © 2017 by ASME
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References

Figures

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Fig. 1

Schematics of die stacking with TSVs, FC, and microbumps (u)

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Fig. 2

Simulation flow schematics

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Fig. 3

The architecture of the analyzed die (a); distribution of global stress components in tier 1 across the subsurface region indicated in (a) by the dashed line (b)

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Fig. 4

Schematic of the bump-induced deformation caused by cooling (a) and a fit between the lateral stress distributions along the die interface caused by a stand-alone bump calculated with the compact model and finite element method simulation (b)

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Fig. 5

Stress component distributions calculated for interconnect with the averaged themomechanical properties (dashed line) and for nonuniform (solid line) interconnect: x corresponds to the routing direction (along metal lines) and y is orthogonal to the routing direction

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Fig. 6

An example of the die-scale simulation results: distributions of stress components across the device layer of tier 1 die. The obtained patterns are due to the effect of FC bumps of 80 μm diameter. The size of the demonstrated region is 1900 × 1300 μm2.

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Fig. 7

Schematics of the cut-line: (a) top view demonstrating device partitioning into cut-lines and (b) vertical slice

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Fig. 8

MOSFET channel stress components calculated prior (dashed line) and after (solid line) relaxation: (a) a layout used for stress simulation, (b) longitudinal, and (c) transversal stress components

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Fig. 9

Mobility variation in NMOS (a) and PMOS (c) with <110> channel orientation caused by bump array. Same variations calculated with the TCAD tool in the small regions of the analyzed layout (b) and (d).

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Fig. 10

Across-die distributions of MULU0 for electrons (a) and holes (b) in the two-tier stack shown in Fig. 3(a)

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Fig. 12

Visualization of detailed analysis result. Variations in transistor characteristics caused by CPI stress.

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Fig. 13

Test structure used for model calibration and calibration results for p-type transistors located at the die edge region

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Fig. 14

Correlation between measured Id and Id reconstructed from strain measurements for transistors located at different distances from TSVs (b) and layout of the test-structure (a) [9]

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Fig. 15

Three TEM lamellae containing transistors in different distance to TSV (a)–(c) and reference lamella (d) on the same sample for measuring of lattice strain under identical experimental conditions (a). Trace of measured points in a defined depth (b).

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Fig. 16

Simulation domains with the lamella (a) and after reconstruction (b)

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Fig. 17

Footprints of the package (1), die (2), and memory (3) (a); least significant bit gradient (b); TCAD-based mobility gradient (c); and stress gradient detected by the hot-spot checker (d) [5,9]

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