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research-article

Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip Package Interaction

[+] Author and Article Information
Valeriy Sukharev

Mentor Graphics Corporation 46871 Bayside Parkway, Fremont, CA 94538
valeriy_sukharev@mentor.com

Jun-Ho Choy

Mentor Graphics Corporation 46871 Bayside Parkway, Fremont, CA 94538
junho_choy@mentor.com

Armen Kteyan

Mentor Graphics Corporation 16 Halabyan Street, Yerevan, Armenia 0038
armen_kteyan@mentor.com

Henrik Hovsepyan

Mentor Graphics Corporation 16 Halabyan Street, Yerevan, Armenia 0038
henrik_hovsepyan@mentor.com

Mark Nakamoto

Qualcomm Technologies, Inc. 5775 Morehouse Drive, San Diego, CA 92121
nakamoto@qti.qualcomm.com

Wei Zhao

Qualcomm Technologies, Inc. 5775 Morehouse Drive, San Diego, CA 92121
weizhao@qti.qualcomm.com

Riko Radojcic

Independent Consultant 850 Beech St., #610, San Diego, CA 92101
rradojcic@yahoo.com

Uwe Muehle

Fraunhofer Institute for Ceramic Technologies and Systems IKTS Maria-Reiche-Strasse 2, D-01109 Dresden, Germany
uwe.muehle@ikts-extern.fraunhofer.de

Ehrenfried Zschech

Fraunhofer Institute for Ceramic Technologies and Systems IKTS Maria-Reiche-Strasse 2, D-01109 Dresden, Germany
ehrenfried.zschech@ikts.fraunhofer.de

1Corresponding author.

ASME doi:10.1115/1.4036402 History: Received December 14, 2016; Revised March 30, 2017

Abstract

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D IC technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in MOSFET/FinFET electrical characteristics is highlighted. A physics-based compact modeling methodology for multi-scale simulation of all contributing components of stress induced variability is described. A simulation flow that provides an interface between layout formats (GDS II, OASIS), and FEA-based package-scale tools, is also developed. This tool can be used to optimize the floorplan for different circuits and packaging technologies, and/or for the final design signoff, for all stress induced phenomena. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements.

Copyright (c) 2017 by ASME
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