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Research Papers

Far Back End of Line Aluminum Stress Reduction Methods for Two-Dimensional/2.5D Fine Pitch Assemblies

[+] Author and Article Information
Krishna Tunga

IBM Corporation,
Hopewell Junction, NY 12533
e-mail: ktunga@us.ibm.com

Thomas Wassick

IBM Corporation,
Hopewell Junction, NY 12533

Maryse Cournoyer

IBM Corporation,
Bromont, QC J2L 1S8, Canada

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received October 2, 2016; final manuscript received March 28, 2017; published online June 14, 2017. Assoc. Editor: Kaushik Mysore.

J. Electron. Packag 139(3), 031004 (Jun 14, 2017) (8 pages) Paper No: EP-16-1110; doi: 10.1115/1.4036368 History: Received October 02, 2016; Revised March 28, 2017

Fine pitch interconnects when used with two-dimensional (2D)/2.5D packaging technology offer enormous potential toward decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased level of stresses within the far back end of line (FBEOL) layers of the chip is the primary concern. Seven different types of 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between −55 °C and 125 °C. Finite element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad interface. Experimental data in conjunction with mechanical modeling were used to determine a safe level of stress at the aluminum to passivation layer interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2D/2.5D package assembly with fine pitch interconnects. Finally, a reliable low stress configuration, which takes into account all the design changes, has been proposed, which is expected to be robust with very low risk of failure within the FBEOL region.

Copyright © 2017 by ASME
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References

Figures

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Fig. 1

Forces acting on the solder interconnect and the aluminum pad

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Fig. 2

Coarse pitch versus fine pitch

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Fig. 3

(a) Schematic of a typical 2D and 2.5D package and (b) schematic of types 1 and 2 lid

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Fig. 4

Peeling between the aluminum pad and the passivation layer

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Fig. 5

Damage extent: (a) light damage and (b) severe damage

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Fig. 6

Global and local models

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Fig. 7

Peeling stress contours at the aluminum pad to passivation layer interface (units in megapascals) for (a) TV1 (coarse pitch) and (b) TV7 (fine pitch)

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Fig. 8

Average peeling stress versus initial fails

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Fig. 9

Effect of increase in solder joint height

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Fig. 10

Effect of increase in solder joint pad size

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Fig. 11

Effect of decrease in aluminum pad size

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Fig. 12

Effect of decrease in aluminum pad thickness

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Fig. 13

Effect of increase in passivation layer thickness

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Fig. 14

Effect of increase in interposer thickness

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Fig. 15

Effect of decrease in laminate thickness

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Fig. 16

Stress comparison for the reliable low stress design

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