0
Research Papers

High-Temperature Interfacial Adhesion Strength Measurement in Electronic Packaging Using the Double Cantilever Beam Method

[+] Author and Article Information
Santosh Sankarasubramanian

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: santosh.sankarasubramanian@intel.com

Jaime Cruz

Department of Mechanical Engineering,
The University of Texas at El Paso,
500 West University Avenue,
El Paso, TX 79968
e-mail: jcruz3@miners.utep.edu

Kyle Yazzie

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: kyle.yazzie@intel.com

Vaasavi Sundar

Department of Mechanical Engineering,
Arizona State University,
P. O. Box 875802,
Tempe, AZ 85287
e-mail: vsundar6@asu.edu

Vijay Subramanian

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: vijay.subramanian@intel.com

Tsgereda Alazar

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: tsgereda.h.alazar@intel.com

Sivakumar Yagnamurthy

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: sivakumar.yagnamurthy@intel.com

Edvin Cetegen

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: edvin.cetegen@intel.com

David McCoy

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: david.c.mccoy@intel.com

Pramod Malatkar

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: pramod.malatkar@intel.com

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 27, 2016; final manuscript received March 24, 2017; published online April 24, 2017. Assoc. Editor: S. Ravi Annapragada.

J. Electron. Packag 139(2), 021003 (Apr 24, 2017) (11 pages) Paper No: EP-16-1149; doi: 10.1115/1.4036356 History: Received December 27, 2016; Revised March 24, 2017

This paper describes the use of the double cantilever beam (DCB) method for characterizing the adhesion strength of interfaces in advanced microelectronic packages at room and high temperatures. Those interfaces include silicon–epoxy underfill, solder resist–epoxy underfill and epoxy mold compounds (EMCs), and die passivation materials–epoxy underfill materials. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon–underfill samples and cracking of solder resist films in solder resist–underfill samples. An asymmetric DCB configuration (i.e., different cantilever beam thickness on top compared to the bottom) was found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Furthermore, in order to characterize the adhesion strength of those interfaces at elevated temperatures seen during package assembly and end-user testing, an environmental chamber was designed and fabricated to rapidly and uniformly heat the DCB samples for testing at high temperatures. This chamber was used to successfully measure the adhesion strength of silicon–epoxy underfill samples at temperatures up to 260 °C, which is the typical maximum temperature experienced by electronic packages during solder reflow. For the epoxy underfills tested in this study, the DCB samples failed cohesively within the underfill at room temperature but started failing adhesively at temperatures near 150 °C. Adhesion strength measurements also showed a clear degradation with temperature. Several other case studies using DCB for material selection and assembly process optimization are also discussed. Finally, fractography results of the fractured surfaces are presented for better understanding of the failure mode.

Copyright © 2017 by ASME
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Fig. 1

Schematic cross section of a flip-chip microelectronic package

Grahic Jump Location
Fig. 2

Custom-made fixture allowed CUF to be carefully dispensed in controlled amounts. The fixture was heated so that capillary action aided in uniform CUF dispense.

Grahic Jump Location
Fig. 3

(a) Schematic of the final silicon–CUF DCB sample and (b) side-view of final sample

Grahic Jump Location
Fig. 4

Stack-up of the DCB sample used to measure solder resist–CUF adhesion strength

Grahic Jump Location
Fig. 5

A cross-sectional view of the mold chase showing the solder resist sample being molded

Grahic Jump Location
Fig. 6

Stack-up of the DCB sample used to measure solder resist–EMC adhesion strength

Grahic Jump Location
Fig. 7

(a) Silicon surface with and without roughening and (b) old and new tab designs

Grahic Jump Location
Fig. 8

The DCB chamber concept was an insulating enclosure, with a window to view the sample. The enclosure would fit over the DCB sample, and attach to a heated base plate.

Grahic Jump Location
Fig. 9

(a) A cross section view of the environmental chamber when it is assembled and (b) final assembled environmental chamber wrapped with polyimide insulation and the heater controllers in the background

Grahic Jump Location
Fig. 10

Load–displacement curve from a typical DCB test illustrating the compliance and critical load values

Grahic Jump Location
Fig. 11

Schematic of DCB samples for measuring adhesion strength of uncontaminated and flux contaminated silicon pieces to CUF

Grahic Jump Location
Fig. 12

DCB adhesion strength results comparing the effect of flux contamination on silicon–CUF adhesion

Grahic Jump Location
Fig. 13

Silicon–CUF adhesion strength variation with temperature for CUF B. The results at 25 °C alone were obtained using asymmetric DCB.

Grahic Jump Location
Fig. 14

Silicon–CUF adhesion strength comparison between two CUF materials at three different temperatures. The results at 25 °C alone were obtained using asymmetric DCB.

Grahic Jump Location
Fig. 15

(a) Top down view of DCB fracture surface on silicon side and (b) fracture surface on underfill side

Grahic Jump Location
Fig. 16

Adhesion strength of die passivation materials, DP1 and DP2, to the same CUF material

Grahic Jump Location
Fig. 17

Comparison of solder resist–EMC and solder resist–CUF adhesion strengths using DCB

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In