0
SPECIAL SECTION PAPERS

High-Temperature Interfacial Adhesion Strength Measurement in Electronic Packaging Using the Double Cantilever Beam Method PUBLIC ACCESS

[+] Author and Article Information
Santosh Sankarasubramanian

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: santosh.sankarasubramanian@intel.com

Jaime Cruz

Department of Mechanical Engineering,
The University of Texas at El Paso,
500 West University Avenue,
El Paso, TX 79968
e-mail: jcruz3@miners.utep.edu

Kyle Yazzie

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: kyle.yazzie@intel.com

Vaasavi Sundar

Department of Mechanical Engineering,
Arizona State University,
P. O. Box 875802,
Tempe, AZ 85287
e-mail: vsundar6@asu.edu

Vijay Subramanian

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: vijay.subramanian@intel.com

Tsgereda Alazar

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: tsgereda.h.alazar@intel.com

Sivakumar Yagnamurthy

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: sivakumar.yagnamurthy@intel.com

Edvin Cetegen

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: edvin.cetegen@intel.com

David McCoy

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: david.c.mccoy@intel.com

Pramod Malatkar

Intel Corporation,
5000 West Chandler Boulevard,
Mail Stop: CH5-157,
Chandler, AZ 85226
e-mail: pramod.malatkar@intel.com

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 27, 2016; final manuscript received March 24, 2017; published online April 24, 2017. Assoc. Editor: S. Ravi Annapragada.

J. Electron. Packag 139(2), 020902 (Apr 24, 2017) (11 pages) Paper No: EP-16-1149; doi: 10.1115/1.4036356 History: Received December 27, 2016; Revised March 24, 2017

This paper describes the use of the double cantilever beam (DCB) method for characterizing the adhesion strength of interfaces in advanced microelectronic packages at room and high temperatures. Those interfaces include silicon–epoxy underfill, solder resist–epoxy underfill and epoxy mold compounds (EMCs), and die passivation materials–epoxy underfill materials. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon–underfill samples and cracking of solder resist films in solder resist–underfill samples. An asymmetric DCB configuration (i.e., different cantilever beam thickness on top compared to the bottom) was found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Furthermore, in order to characterize the adhesion strength of those interfaces at elevated temperatures seen during package assembly and end-user testing, an environmental chamber was designed and fabricated to rapidly and uniformly heat the DCB samples for testing at high temperatures. This chamber was used to successfully measure the adhesion strength of silicon–epoxy underfill samples at temperatures up to 260 °C, which is the typical maximum temperature experienced by electronic packages during solder reflow. For the epoxy underfills tested in this study, the DCB samples failed cohesively within the underfill at room temperature but started failing adhesively at temperatures near 150 °C. Adhesion strength measurements also showed a clear degradation with temperature. Several other case studies using DCB for material selection and assembly process optimization are also discussed. Finally, fractography results of the fractured surfaces are presented for better understanding of the failure mode.

A typical flip-chip microelectronic package assembly consists of a silicon die attached to a substrate through copper-solder interconnects with a capillary underfill (CUF) in between the interconnects that provide mechanical rigidity. As shown in Fig. 1, there are many interfaces present primarily related to the CUF, such as silicon die sidewall–CUF, solder resist–CUF, and die passivation–CUF. Modern microeletronic packages have multiple materials and components such as epoxy mold compounds and stiffeners, attached to the package [13].

During manufacturing, in the assembly process, and end-user conditions, simulated by testing, these packages are exposed to high temperatures, thermal cycling, humidity, or a combination of these loads. These induce thermomechanical stresses at the various interfaces of the package, driven by the differences in mechanical properties between the materials that make up the interface. These stresses, in turn, could lead to delamination at these interfaces which is undesirable as the delamination could propagate and cause overall package failure [4,5]. The lack of an accurate adhesion strength metrology has made it challenging to predict reliability performance of new materials and processes. Without a good metrology, material selection and assembly process optimization require expensive assembly builds, followed by reliability testing which leads to long development times.

Several methods exist to determine the adhesion strength of interfaces. Some of the most common ones are pull test, scratch test, blister test, button shear test, peel test, and beam bending test [6]. Each method has its advantages and disadvantages with respect to the level of difficulty of sample preparation and/or data analysis. Pull tests, scratch tests, button shear, and peel tests all offer simple sample preparation but each has certain disadvantages or limitations. Pull test is a strength-of-materials type test that can be sensitive to defects or misalignment [7], while scratch testing lends itself more to testing hard or brittle thin films that can be easily deposited on test coupons. Button shear results tend to show high variation while peel testing is suitable for thin, nonbrittle films and is only semiquantitative. Blister tests have the advantage of being able to yield quantitative adhesion data, but sample preparation is quite difficult. Beam bending methods, such as double cantilever beam, also require difficult sample preparation, but they utilize fracture mechanics to extract quantitative adhesion data with less variation compared to button shear.

Another consideration in method selection is the mode mixity of each adhesion test method. An interface can be subjected to mode I (tensile), mode II (shear), mode III, or a combination [6,8]. Unlike in a homogeneous material, a crack at a bimaterial interface always sees a combination of these modes irrespective of the external loading. The ratio of these modes is referred to as the mode mixity, and it influences the measured adhesion strength [9]. When the mode-mixity value is low, the crack sees predominantly mode I loading and when the mode-mixity value is high it sees mode II loading. Typically, an interface will fail more easily in mode I, so a test designed for mode I will be more sensitive. Button shear and blister tests are examples where the external loading is predominantly mixed mode which strongly influences the mode-mixity of the crack and so the data generated from these tests show large variation.

Finally, the choice of which test method to employ also depends on the nature of the materials involved as that would affect the possibility of sample preparation, and the dimension of the sample that can be fabricated. For example, peel test requires a thin film (micrometer–millimeter thickness range) of material which is flexible and/or ductile attached (deposited or bonded with an adhesive) to a substrate material. This precludes the use of peel test for interfaces involving brittle materials. On the other hand, double cantilever beam (DCB) test requires one material that can be cut into cantilever beams and then be bonded together using the other interface material. Materials which are plated or deposited cannot be tested using the DCB test method.

In the DCB test, the interface of interest is held between two elastic substrates which are then pulled apart, in tension, to slowly grow a precrack previously introduced at the interface. From the resulting load–displacement data, the critical mode I strain energy release rate (GIC) can be calculated at multiple locations along the interface. The strain energy release rate is the energy dissipated per unit area of the newly created surface during fracture. Since the interface toughness tested for at low mode-mixity is lower than at other mode-mixity factors typically experienced by interfaces in real units [6,8], the DCB test provides data which envelope (in a lower-bound sense) the loading seen in a real package. Another salient feature of DCB is the ease of producing a mixed-mode loading condition during the test by using cantilever beams of unequal thickness [7,10]. This test is called asymmetric DCB. Finally, multiple values of GIC can be extracted from a single DCB sample, which reduces the number of samples needed [11,12].

For these reasons, the DCB test was chosen as the metrology to help address package technology developments. Many key challenges had to be overcome to successfully develop a mature DCB metrology. The challenges varied based on the interface being studied. In the case of silicon–CUF, silicon coupons were prone to premature failure from silicon cracking due to edge defects. This was addressed with a unique sample geometry that created crack growth away from sample edges. Similarly, since solder resist films were brittle, in order to make solder resist–CUF samples without damaging the film, the films were laminated to a block of underfill which acted as an elastic substrate. Further sample preparation improvements were performed in order to eliminate voids in the adhesive layer. The sample preparation techniques are discussed in Sec. 2.

An additional capability that was developed in this study is the ability to measure adhesion strength using DCB at elevated temperatures. During package assembly and reliability testing, microelectronic packages can experience temperatures as high as solder reflow (∼260 °C) and as low as −55 °C [13]. In order to accurately gauge how the interfaces within these packages fail at these temperatures, it is important to measure adhesion strength through this entire temperature range. Another reason to perform DCB testing at high temperatures is the potential to induce adhesive fails at these temperatures. A DCB sample can fail in one of three modes: (1) adhesive (at the interface of interest), (2) cohesive (within the adhesive), or (3) brittle (substrate cracking). While comparing the adhesion strength of two CUF materials to silicon for example, if both of them fail cohesively at room temperature, it would not be possible to conclude which underfill has the higher adhesion. While asymmetric DCB is one solution to induce adhesive fails at room temperature, DCB testing at high temperatures can also be used as a method to induce adhesive fails in samples that fail cohesively at room temperatures. This would allow rank ordering of underfills and other materials based on adhesive strength.

In order to do DCB testing at various temperatures, an environmental chamber was developed to fit around the load frame used for DCB testing. Section 3 describes the design and fabrication of this chamber. Section 4 describes the DCB testing procedure, while Sec. 5 presents results from various studies done using the DCB metrology. Section 6 summarizes the paper and discusses future development areas.

This section highlights the DCB sample preparation techniques that were developed for each interface of interest. As will be explained, each interface had its own set of challenges and hence required different sample preparation techniques.

Silicon–Capillary Underfill Double Cantilever Beam Sample Preparation.

Blank silicon wafers were cut into 12 mm × 50 mm rectangular pieces using a dicing saw. The silicon beams were cleaned with acetone, isopropyl alcohol (IPA), and then dried with oil-free air to remove organic residues. One side of silicon surface was masked with polytetrafluoroethylene tape and a thin gold film was sputter-coated onto it to create a precrack. The sputter-coating was also applied along the sides of the silicon surface to prevent the edge chipping caused by dicing from interfering with the DCB test. The masking tape was peeled off and the exposed silicon was again cleaned with IPA. This exposed region was the region of interest for measuring the adhesion strength between silicon and CUF. The gold-coated silicon beam was firmly placed on top of another piece of clean silicon with a 50 μm polyimide film at either end as spacers. Using a custom built apparatus equipped with a syringe and needle assembly, underfill was carefully dispensed into the 50 μm gap with the help of capillary action, as shown in Fig. 2.

During development of the dispense process, a high-sensitivity infrared camera was used to monitor the CUF flow front. This enabled the identification of voids in the underfill since they could be clearly observed in the infrared image. This helped optimize the dispense conditions need for eliminating voids with each underfill. After dispense, the specimens were then placed in an oven to cure the CUF material. After the curing process, loading tabs were bonded to the DCB specimens to enable testing of these specimens in mode I. A schematic of the final sample is shown in Fig. 3(a) and side-view of an actual sample is shown in Fig. 3(b).

For testing the silicon–CUF interface, both symmetric and asymmetric DCB samples were created. For symmetric DCB, both pieces of silicon had the same thickness, around 800 μm (referred to as “full thickness”). For asymmetric DCB, the piece of silicon on which the precrack was sputtered was picked from a thinned silicon wafer, while the other piece was maintained at the full thickness of 800 μm. As will be discussed in Sec. 4, a nominal thickness of 300 μm for the thinner silicon was found to be ideal for obtaining adhesive failures without silicon cracking.

Die Passivation–Capillary Underfill Double Cantilever Beam Sample Preparation.

Die passivation materials such as silicon nitride and polyimide are available in the form of wafers where the passivation material is a thin blanket layer, typically around 1 μm thick, on the silicon wafers. These wafers could be cut similar to the blank silicon wafers, and hence, the sample preparation procedure for die passivation–CUF DCB samples was identical to the silicon–CUF DCB sample preparation procedure described in Sec. 2.1.

Solder Resist–Capillary Underfill Double Cantilever Beam Sample Preparation.

The solder resist used for DCB measurements was a brittle, thin film, about 20 μm thick which made it very challenging to handle without breaking it. Mahan et al. [14] used a modified version of the single cantilever beam method [15] to handle this challenge. In this study, the film was first attached to an elastic coupon in order to be able to create a sample where the solder resist–underfill interface could be pulled apart without cracking the resist. A block made out of fully cured underfill material itself was used to make the elastic substrate, henceforth referred to as an underfill block, and the same underfill material in uncured form was used as an adhesive to attach the solder resist film to the underfill block.

The solder resist film was attached to an underfill block of dimensions 50 mm × 20 mm × 5 mm after which the sample was heated in an oven to cure the underfill adhesive. Once this lamination process was completed, a gold precrack layer was sputtered on to the top of the solder resist to about 15 mm length. This created one half of the DCB sample. This half was attached to a second underfill block using uncured underfill as the adhesive once again. A 50 μm polyimide film was used as a spacer between the blocks. Additionally, the second block was oversized by about 5 mm on all sides compared to the first block so as to provide sufficient area for excess underfill adhesive to overflow.

This sandwich was clamped together and once again heated in an oven to cure the second layer of underfill adhesive. After cure, the sandwiched blocks were cut into three individual samples, 5 mm wide, and tabs attached at the top and bottom. Finally, a blade was used to cut an additional mechanical notch on top of the precrack to facilitate the initial crack propagation. Figure 4 shows the stack-up of the final DCB sample used to measure the solder resist to CUF adhesion strength. The final dimensions of the top and bottom underfill block were 50 mm × 5 mm × 5 mm. In this figure, the interface of interest is between underfill adhesive layer 2 and the side of the solder resist film containing the gold precrack.

Solder Resist–Epoxy Mold Compounds Double Cantilever Beam Sample Preparation.

Epoxy mold compounds (EMCs) are used in place of CUF materials to reinforce solder joints in some packages, typically due to cost and warpage considerations. Packages with EMCs can also be overmolded where the EMC is also flown over the die and completely encapsulates the die. The net result is that similar to CUF materials, EMCs also come in contact with multiple materials in a microelectronic package [13].

Epoxy mold compounds are applied to a package by flowing mold pellets under heat and pressure inside a mold chase. The mold chase used for this study had a cavity of dimensions 75 mm × 15 mm × 6.25 mm. The sample preparation technique used to make solder resist–EMC DCB samples was similar to the technique used to make solder resist–CUF DCB samples. The solder resist film was attached an underfill block of dimensions 50 mm × 12 mm × 5 mm. This block was narrower than the 20 mm wide block used for making the solder resist–CUF samples, since the block had to fit inside the mold chase. A 1 mm thick piece of polytetrafluoroethylene was used as a spacer underneath the block in order to limit the EMC thickness to about 250 μm. The layout of the sample inside the mold chase is shown in Fig. 5.

Once the molding process is completed, the molded piece is removed from the mold chase and cured inside an oven to cure the EMC material. This creates the bottom half of the molded sample. Finally, a second underfill block is attached to the EMC layer using an adhesive (underfill itself in this study) to create the final DCB sample as shown in Fig. 6.

Loading Tab Detachment During High-Temperature Double Cantilever Beam Testing.

The final sample preparation step prior to testing for all the DCB samples discussed in this section was to attach loading tabs to the sample using an adhesive so as to enable testing of the samples in mode I. The testing procedure is discussed in Sec. 4, while Sec. 5 discusses results from DCB testing of silicon–CUF samples at elevated temperatures. During this elevated temperature testing, the loading tabs were found to frequently detach from the samples. Typically, only one of the tabs would detach and it detached before any opening of the DCB sample occurred. This meant that no adhesion data could be measured from these samples. Furthermore, once the tab detached, the remnant adhesive on the silicon surface had to be carefully cleaned to avoid breaking the silicon before the tab could be reattached. This process was time consuming and was not always successful, i.e., the reattached tab would once again detach during testing. An additional concern with this “rework” process was that since the sample had already been heated once to the testing temperature, it was unclear if this second heating cycle would affect the adhesion values in any way.

This tab detach issue did not occur during room temperature testing; hence, it was concluded that the detachment occurred because the adhesive used to attach the tabs to the silicon weakened significantly at elevated temperatures. Two improvements were made to this tab detachment problem: (1) the surface of the silicon where the tabs were to be attached were roughened gently and (2) a new tab design was used with a higher surface area for attaching the tab to the silicon. Images of the silicon before and after roughening are shown in Fig. 7(a), while the old and new tab designs are shown in Fig. 7(b).

The purpose of the environmental chamber was to enable DCB testing from temperatures as low as −55 °C to as high as 260 °C. The DCB samples were tested using a commercially available load frame, to evaluate interface strength, consisting of a low-noise load cell and a screw-driven actuator. This assembly was connected to a computer to record load and displacement. Because of the compact nature of the load frame, one of the primary design considerations for the environmental chamber was the amount of space occupied. In the smallest dimension, the maximum available space was less than 100 mm. A survey of commercially available small ovens and environmental chambers did not identify one which would fit within the space available in the load frame. Hence, a chamber was designed and fabricated in-house.

In terms of operational requirements, a temperature uniformity of less than 10 °C across the length of the sample was specified as the primary requirement. It must be noted that the samples tested in this chamber typically had a maximum length of about 75 mm. Next, a heating rate of at least 10 °C/minute was required in order to enable a fast throughput time for high-temperature testing. Finally, the chamber had to be safe and ergonomic to use as well as easy to install and uninstall in order to rapidly switch between room temperature and high-temperature testing. Figure 8 shows the concept of the DCB chamber.

The final design consisted of an aluminum heater baseplate attached to another baseplate made of a thermally insulating material developed for high-temperature environments. The aluminum heater base plate had three cartridge heaters of half-inch diameter embedded within the aluminum. This heater base plate was the main heat source, providing heat from the bottom. The heat of this base plate was contained using a rectangular cover made of the same thermally insulating material as the baseplate. This cover had aluminum side heater plates with two quarter-inch cartridge heaters, each mounted on the inner walls on two opposite sides, as shown in Fig. 9(a). The side heaters served to improve temperature uniformity of the sample in the vertical direction. The base plate and the side heaters were controlled by two separate controllers. A viewing window was added to the front wall of the cover to enable the sample to be viewed during testing. The final assembled dimensions of the chamber were ∼ 90 mm × 100 mm with a height of 190 mm. The entire chamber was wrapped with a polyimide insulation to allow it to be safely handled.

Finally, perforated connecting rods were fabricated and used to connect the load cell, the actuator, and the sample clevises which hold the DCB sample inside the chamber. The perforated rods minimized heat transfer to the load frame and load cell to minimize thermal drift of the load cell. The chamber was also fitted with an insulated connecting hose for the option of connecting it a liquid nitrogen gas tank to cool the chamber down to subzero temperatures. At the time of this study, the chamber had been evaluated only for high-temperature testing as discussed in Secs. 4 and 5. Future testing will also focus on testing at subzero temperatures where initial testing indicated that the chamber can reach temperatures down to −40 °C. Figure 9(b) shows an image of the environmental chamber when it is placed within the load frame used for DCB testing.

The environmental chamber was tested and found to meet the design and heating rate requirements described earlier. In order to ensure the thermal uniformity specification of 10 °C across the length of the sample, two thermocouples were attached to each DCB sample during testing. One was attached near the top of the sample and the other near the bottom. For each test temperature of interest, the two heater controllers were adjusted individually until both the top and the bottom thermocouples read within ±3 °C of the target temperature. This was a required one-time calibration of the heater controllers for each test temperature of interest.

The DCB samples were tested using a commercially available load frame to evaluate interface strength, consisting of a low-noise load cell and a screw-driven actuator. This assembly was connected to a computer to record load and displacement. The samples were held on the load frame using clevis grips and the load tabs.

During the test, the specimens were displaced at a rate of 5 μm/s, which was slow enough to be considered to be quasi-static. The initial delamination typically occurred at the side of the interface containing the precrack. The specimens were loaded at constant rate until local crack propagation was observed resulting in a sharp drop in the load–displacement curve. At this point, the specimen was unloaded and then reloaded until the next local crack propagation was observed. This load–unload–reload procedure was repeated until complete failure was observed. A typical load–displacement curve recorded during DCB testing is shown in Fig. 10.

Once the test was completed, the critical mode I strain energy release rate (GIC) was calculated at each instance of local crack propagation. In other words, multiple values of GIC can be calculated for each sample. The calculation procedure is described in Ref. [11]:

  1. (1)Calculate compliance C and critical load (Pc) values from the load–displacement data at each instance of crack propagation, as shown in Fig. 10.
  2. (2)For each value of C and Pc, calculate the crack length (a) based on the following equations. The compliance, C, and crack length, a, at each crack growth location are related according to [11] Display Formula
    (1)C=i=top,bottom{1EIiλi3[λi3(2a32d3)3+2λia+2λi2a2+1]+(3(ad)2bGhi)}
    where d is half the length of the loading tabs, while E and G are, respectively, the elastic and shear modulus of the substrate used to make the DCB sample. λi is defined for each half of the DCB sample as Display Formula
    (2)λi=ki4EIi4
    where Ii is the moment of inertia for each half of the DCB sample, Display Formula
    (3)Ii=bhi312
    and ki is the foundation modulus of each half of the DCB sample Display Formula
    (4)ki=2Ebhi
    where b is the width of the DCB sample and hi is the thickness of each half of the DCB sample. An iterative procedure programmed in matlab was used to solve for the crack length a from Eq. (1). It must be noted that the above equations for calculating crack length are applicable to both symmetric DCB (htop = hbottom) as well as to asymmetric DCB (htop ≠ hbottom).
  3. (3)Once the crack length is known, multiple analytical solutions are available in literature for symmetric DCB [11,12,16] to calculate critical strain energy release rate (GIC) for each crack length (a)—critical load (Pc) pair. These analytical solutions gave almost identical results for GIC (within 0.2%). Asymmetric DCB produces a mixed-mode loading condition at the interface (mode I + mode II) and analytical solutions are available to calculate both the total critical strain energy release rate (GC, tot) as well for mode I (GIC) [12]. For isotropic materials, the total and mode I GC at each crack location are given by [12] Display Formula
    (5)GC, tot=6Pc2a2Eb2h3[1+(hH)3](1+0.667Bha)2
    Display Formula
    (6)GIC=6Pc2a2Eb2h3[1+(hH)3]sin2ϕ(1+0.667B1ha)2
    where h and H are the smaller and larger of the two beam thicknesses, while B, B1, and ϕ are given by Display Formula
    (7)B=1.1200.695(hH0.585)2
    Display Formula
    (8)B1=1+0.546(1hH)
    Display Formula
    (9)ϕ=[0.574+0.033(hH)+0.805(hH)20.413(hH)3](π2)

It was verified for symmetric DCB that both GC,tot and GIC from Eqs. (5) and (6) gave identical results. These equations assume linear elastic behavior of the substrates used to make the DCB samples. An analysis for elastic–plastic materials is provided in Ref. [17].

After testing, the failed samples were inspected to identify the failure mode. For each interface that was tested, the observed failure modes were either: (1) adhesive (at the interface of interest), (2) cohesive (within the adhesive), or (3) brittle (typically observed only for silicon-based DCB samples as silicon cracking). Samples that showed adhesive failures were desired as they enabled rank ordering of materials. DCB yield was defined as the percentage of samples showing adhesive failures.

This section discusses some of the applications of the DCB samples created using the sample preparation methods described in Sec. 2 and tested using the procedure described in Sec. 4. Unless mentioned otherwise, symmetric DCB samples were used for testing. The critical mode I strain energy release rate (GIC) values presented here were normalized relative to the lowest GIC value for that study. Finally, as mentioned in Sec. 3, multiple values of GIC can be calculated for each DCB sample.

Effect of Flux Materials on Silicon–Capillary Underfill Adhesion Strength.

In the chip-attach process in flip-chip microelectronic packaging, the silicon chip (die) is attached to a substrate by forming joints between solder balls on the substrate and copper bumps on the chip. The chip-attach process uses flux materials to clean oxides on the solder balls in order to enable electrically functional joint formation between the solder balls and the copper bumps [1,18]. After chip attach, an underfill material is flown through these joints by capillary action, in order to stabilize the joints. The flux materials used in chip-attach tend to leave behind a residue, which if not cleaned thoroughly could impact adhesion between the capillary underfill material and silicon sidewall.

The DCB metrology was used to study the potential degradation in adhesion between silicon and underfill as a result of flux residue. Two sets of silicon–CUF DCB specimens were produced, both consisting of a silicon–CUF–silicon stack, using the sample preparation procedure described in Sec. 2.1. In one set, prior to creating the DCB specimen, the silicon piece with the precrack was subjected to a simulated chip-attach in order to contaminate the side containing the precrack with flux residue. For the control set, no contamination was done. A schematic of the two sets of samples is shown in Fig. 11.

Samples created using this method was used to test the effect of two different flux materials, designated flux A and flux B, on silicon–CUF adhesion, with a no-flux leg as control. The results from the DCB testing are shown in Fig. 12. Multiple samples were tested for each case and the results shown in the figure only show samples that failed adhesively. It is clear from the results that flux contamination can reduce the silicon to underfill adhesion by more than 50% which has significant implications for the reliability of these packages.

A smaller difference can be seen between the two fluxes. For this experiment, the amount of flux residue that was transferred to the silicon during the simulated chip-attach was not quantified. Hence, it was not possible to conclude whether the difference in adhesion between the two flux materials was due to inherent chemical differences between the two fluxes or due to different amounts of flux residue being transferred to the silicon—the latter could be a function of the flow behavior of the flux.

With “DCB yield” defined as the percentage of samples that exhibited pure adhesive failures, typical yields were in the range of 50% for the symmetric DCB samples above, with cohesive failures inside the underfill the main source of “yield loss.” Asymmetric DCB samples were found to have improved yield, i.e., a higher percentage of samples showing adhesive failures, when the precrack was applied on the thinner silicon. Two thicknesses were attempted for the thin silicon piece in the asymmetric DCB sample, 300 μm and 500 μm, with the other half of the DCB sample being a full-thickness (800 μm thick) piece of silicon. It was found that the yield with asymmetric DCB samples containing 500 μm silicon was not significantly better compared to symmetric DCB samples (around 50% adhesive). With 300 μm silicon though, yields improved to the 70–80% range. It is suspected that using silicon thinner than 300 μm is likely to cause brittle silicon failures.

As explained in Sec. 3, with asymmetric DCB, the interface is subjected to mixed-mode loading (combination of mode I + mode II). Analytical models in existing literature [12] were used to separate out the critical strain energy release rate values for mode I and mode II with the mode I value (GIC), and then used to quantify the adhesion strength of the interface for reasons described in Sec. 1. A full characterization of the asymmetric DCB test is in progress for the silicon–CUF interface with particular focus on the repeatability of the GIC value for different silicon thicknesses as well as understanding the thickness window available where adhesive failures dominate, i.e., high DCB yields exist. It is expected that at the lower thickness end of this window, brittle silicon cracking would dominate, while cohesive failures will dominate the upper end.

Silicon–Capillary Underfill Adhesion Strength Variation with Temperature.

This section discusses some of the adhesion results obtained using the environmental chamber for DCB testing. Two case studies are discussed here: (1) the change in adhesion strength of the silicon–CUF interface with temperature for a single CUF material and (2) a comparison of the adhesion strength of two different CUF materials across a range of temperatures. The two CUF materials considered in this study are designated CUF A and CUF B. Both materials had a glass transition temperature (Tg) of around 130 °C, which as explained later, was an important material property that helped understand the observed DCB failure modes with temperature. Other material properties such as thermal expansion coefficients and elastic modulus were broadly similar for the two materials.

The silicon–CUF adhesion strength was measured for CUF B, at nine different temperatures: 25 °C, 100 °C, 125 °C, 150 °C, 180 °C, 200 °C, 220 °C, 240 °C, and 260 °C. It was found that for this CUF material, the DCB samples failed cohesively within the CUF layer at 25 °C, 100 °C, and 125 °C, while they failed adhesively at 150 °C and above. This indicates that, at least up to 125 °C, the cohesive strength of the CUF materials is lower than the silicon–underfill adhesive strength. Conversely, at 150 °C and above, the adhesive strength is weaker than the cohesive strength of the underfill. This could be because the Tg of CUF A was around 130 °C causing a significant drop in adhesion at these temperatures which are above the Tg.

Hence, the silicon–CUF adhesive strength could not be determined at temperatures up to 125 °C without resorting to other techniques such as asymmetric DCB. For this case study, asymmetric DCB was performed at 25 °C alone and adhesive failures were obtained. Those results are plotted in Fig. 13 along with the silicon–CUF adhesive strength at 150 °C and above obtained using symmetric DCB.

The results show a clear drop in adhesion with temperature. The mean adhesion strength drops by around 25% between 25 °C and 150 °C with a further 55% drop between 150 °C and 180 °C. Above 180 °C, the adhesion strength remains fairly low. It is suspected that the low adhesion at 180 °C is because the underfill is well above its Tg at that temperature. Additionally, it can be noticed that there is a significant sample-to-sample variation and within-sample variation. Further characterization is needed to fully understand the factors affecting this variation. However, one general observation is that the variability is much tighter with low adhesion strengths, such as with the adhesion at 180 °C.

Next, the silicon–CUF adhesion strength was compared for two materials, CUF A and CUF B, at three different temperatures: 25 °C, 150 °C, and 180 °C. Similar to CUF A, CUF B also failed cohesively at 25 °C and asymmetric DCB had to be used to obtain adhesive failures. At 150 °C and 180 °C, CUF B failed adhesively, which, as explained before, could be because the material is above its Tg at those temperatures and, therefore, has low adhesion strength. The resulting adhesion values are plotted in Fig. 14.

Similar to CUF A, CUF B also shows a drop in adhesion with temperature—there is a 35% drop between 25 °C and 150 °C and a much sharper 75% drop from 150 °C to 180 °C. At all temperatures, CUF B has a higher adhesion to silicon compared to CUF A. CUF B has almost a three-times higher adhesion to silicon compared to CUF A at 25 °C and about twice the adhesion at 150 °C. The differences are much smaller at 180 °C, which is well above the Tg of both CUF materials—still, CUF B has about a 30% higher adhesion than CUF A at this temperature.

One more important observation from this plot is that the trend in adhesion remains consistent with temperature, i.e., CUF B has higher adhesion to silicon compared to CUF A at all the tested temperatures. This means that if rank ordering of CUF materials based on adhesion is needed, it could be sufficient to do the testing at just one temperature as long as adhesive fails are obtained at that temperature. It is, however, important to verify this conclusion with more CUF materials and also at other interfaces before considering it universal.

Silicon–Capillary Underfill Double Cantilever Beam Specimen Fractography.

The fracture surfaces from the silicon–underfill DCB test were examined with a scanning electron microscope (SEM) to understand the failure better. Figure 15 shows SEM images of a failed sample. Figure 15(a) shows the typical top down view from the silicon side of the fracture surface. A very thin layer of underfill residual can be seen on top of silicon, indicating the failure was not purely adhesive between silicon and underfill, although the crack path was very close to silicon–underfill interface. Figure 15(b) is the fracture surface on the underfill side. The roughness of the surface was consistent with the silicon side observation that the crack was not purely separated between silicon and underfill but was through underfill close to silicon. In short, while the failure is mainly adhesive, there was a thin film of underfill residue on the silicon side of the fracture surface, indicating that purely adhesive failure is not common. Finally, small dimples of about 100 nm diameter can be observed on both sides of the fracture surfaces, which could be from the outgassing of CUF during curing.

Die Passivation–Capillary Underfill Double Cantilever Beam Testing Results.

Microelectronic packages use materials such as silicon nitride, silicon oxide, and polyimide different as die passivation materials. As can be seen from Fig. 1, the die passivation comes into contact with the underfill that is dispensed in between the copper-solder joints. Any delamination that occurs between the passivation material and underfill could propagate during package assembly and reliability testing, eventually leading to package failure. Hence, the selected underfill material is required to have good adhesion to the die passivation material as well. Alternately, if the die passivation material is changed, the new material is required to have high adhesion to the underfill.

In this case study, the adhesion of two different die passivation materials, DP1 and DP2, to a CUF material, CUF C, was measured using DCB testing. As mentioned, in Sec. 2.2, the sample preparation procedure used for this interface was identical to the procedure for the silicon–CUF interface. The results are shown in Fig. 16. The DCB testing clearly shows that the adhesion of CUF C to DP2 is four to five times higher than the adhesion to DP1.

Solder Resist–Capillary Underfill and Epoxy Mold Compounds Double Cantilever Beam Testing Results.

The adhesion strength of two different solder resist materials, labeled SRF1 and SRF2, to CUF materials and EMCs, was measured using the DCB test. The testing was performed at room temperature and the results are plotted in Fig. 17.

At the time of this publication, only a limited number of samples were used for the solder resist–EMC adhesion data collection. The results show that for both solder resist materials, the adhesion to CUF materials (CUF B or CUF D) was significantly higher than the adhesion to any of the EMC materials. This indicates that molded packages are at a higher risk of delamination at the solder resist interface when compared to CUF packages.

Another observation is that for both CUF materials, the adhesion strength with SRF2 is 50% lower compared to the strength with SRF1. The adhesion strength did not have a significant dependence on the underfill material. It is clear that using SRF2 as the solder resist material would pose a higher risk for package reliability compared to SRF1. This DCB dataset, therefore, provides very clear guidelines for material selection based on adhesion strength.

With the adoption of new technologies into microelectronic packages and the continuous quest for low-cost and better packaging materials and processes, the study of adhesion strength of interfaces in microelectronic packages has become important. Poor interfacial adhesion means poor package yield during the assembly process and under real-world use conditions. This paper discussed the use of the DCB adhesion metrology to measure adhesion strength of interfaces like silicon–CUF, die passivation materials-CUF, solder resist–CUF, and solder resist–EMC. In actual microelectronic packages, the mode of delamination at an interface can be mixed. However, DCB, having low mode mixity, provides the lowest value of interfacial toughness giving experimental sensitivity (by eliminating the impact of mixed-mode loading) necessary to detect process and material impacts on adhesion unlike in blister or button shear tests. Asymmetric DCB was found to improve the adhesive yield for silicon–underfill DCB testing.

This paper also discussed the design and fabrication of an environmental chamber for performing DCB adhesion testing across a range of temperatures. This was important because microeletronic packages are subjected to temperatures as low as −55 °C to as high as 260 °C during package assembly and reliability testing. This chamber was capable of heating samples up to the required temperature at a rate of 10 °C/min and maintaining a temperature uniformity within 10 °C across the sample. Loading tabs were found to frequently detach during high-temperature testing. This issue was resolved by roughening the area of the sample where the tab was attached as well as using tabs with higher surface for attachment.

Multiple case studies demonstrated the use of this metrology for material selection in microelectronic packages. This includes chip-attach flux material selection, CUF material selection based on adhesion to silicon, die passivation selection based on addition to CUF as well as solder-resist and EMC selection.

Two case studies where the environmental chamber was used to perform high-temperature DCB testing on silicon–CUF samples were presented. The results from the case studies showed that silicon–CUF adhesion drops with temperature, with a large drop seen when adhesion is tested well above the Tg of the CUF materials. Such results aid CUF material selection by verifying that the selected underfill has the highest adhesion not just at room temperature but also across the range of temperatures that a typical microelectronic package is subjected to.

One of the other advantages of high-temperature testing was the ability to induce adhesive failures, when room temperature adhesion testing only resulted in cohesive fails. If room temperature adhesion testing of two underfill materials to silicon, for example, results in cohesive fails for both materials, it does not give any information about the relative adhesive strength of those two materials. Testing at high temperatures and inducing adhesive fails enables differentiating between the two materials based on adhesion strength. Since the adhesion trend did not change with temperature for the two CUF materials discussed in Sec. 5.2, it could be sufficient to do the testing at just one temperature as long as that adhesive fails are obtained at that temperature. However, this conclusion needs to be verified with a larger material set and for other interfaces as well.

The design of the environmental chamber allows high-temperature DCB testing to be easily extended to other interfaces of interest in microelectronic packages such as silicon–epoxy mold compound and die passivation materials–underfill. These interfaces will be the focus of future testing along with testing at subzero temperatures which the chamber is enabled for.

The authors would like to acknowledge the outstanding contributions to this study from the following people, all from Intel® Corporation: Mark Allen, Joe Bautista, Mike Drake, Don Erickson, Suriya Ramalingam, Liwei Wang, Nachiket Raravikar, Deepak Arora, Yonghao Xiu, Al Lopez, Yiqun Bai, Nisha Ananthakrishnan, Alan Overson, Bob Dalpe, Rodney Wells, Patrick Nardi, Beverly Canham, Dilan Seneviratne, Bharat Penmecha, Jon Atkins, Pilin Liu, and Gaurang Choksi.

  • a =

    crack length

  • b =

    width of the DCB sample

  • B, B1, ϕ =

    functions of the smaller and larger beam thicknesses

  • C =

    compliance of the DCB sample

  • d =

    half the length of the loading tabs

  • E =

    elastic modulus of the substrate used to make each half of the DCB sample

  • G =

    shear modulus of the substrate used to make each half of the DCB Sample

  • GC, tot =

    total critical strain energy release rate

  • GIC =

    critical strain energy release rate in mode I

  • h =

    smaller beam thickness between the top and bottom beams

  • H =

    larger beam thickness between the top and bottom beams

  • hi =

    thickness of each half of the DCB Sample (i = top, bottom)

  • Ii =

    moment of inertia of each half of the DCB sample (i = top, bottom)

  • ki =

    foundation modulus of each half of the DCB sample

  • PC =

    critical load for crack growth

  • Tg =

    glass transition temperature

  • λi =

    a function of foundation modulus, elastic modulus and moment of inertia of each half of the DCB sample (i = top, bottom)

Tong, H. , Lai, Y. , and Wong, C. P. , 2013, Advanced Microelectronic Packaging, Springer, New York.
Sun, P. , Xu, C. , Liu, J. , Geng, F. , and Cao, L. , 2016, “ Flip Chip CSP Assembly With Cu Pillar Bump and Molded Underfill,” 17th International Conference on Electronic Packaging Technology (ICEPT), Wuhan, China, Aug. 16–19, pp. 807–811.
Joshi, M. , Pendse, R. , Pandey, V. , Lee, T. K. , Yoon, I . S. , Yun, J. S. , Kim, Y. C. , and Lee, H. R. , 2010, “ Molded Underfill (MUF) Technology for Flip Chip Packages in Mobile Applications,” 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1–4, pp. 1250–1257.
Sinha, T. , Davis, T. J. , Lombardi, T. E. , and Coffin, J. T. , 2015, “ A Systematic Exploration of the Failure Mechanisms in Underfilled Flip-Chip Packages,” IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, May 26–29, pp. 1509–1517.
Paquet, M. C. , Sylvestre, J. , Gros, E. , and Boyer, N. , 2009, “ Underfill Delamination to Chip Sidewall in Advanced Flip Chip Packages,” 59th Electronic Components and Technology Conference (ECTC), San Diego, CA, May 26–29, pp. 960–965.
Lacombe, R. , 2006, Adhesion Measurement Methods: Theory and Practice, CRC Press, Boca Raton, FL.
Pearson, R. , 2014, “ Adhesion Fundamentals for Microelectronic Packaging,” IMAPS 10th International Conference and Exhibition on Device Packaging, Fountain Hills, AZ, Mar. 11–13.
da Silva, L. F. M. , Dillard, D. A. , Blackman, B. R. K. , and Adams, R. D. , 2012, Testing Adhesive Joints, Wiley-VCH, Weinhem, Germany.
Hutchinson, J. W. , and Suo, Z. , 1991, “ Mixed Mode Cracking in Layered Materials,” Adv. Appl. Mech., 29, pp. 63–191.
Li, H. , Kobrinsky, M. J. , Shariq, A. , Richards, J. , Liu, J. and Kuhn, M. , 2013, “ Controlled Fracture of Cu/Ultralow-k Interconnects,” Appl. Phys. Lett., 103(23), p. 231901. [CrossRef]
Dai, X. , Brillhar, M. V. , and Ho, P. S. , 2000, “ Adhesion Measurement for Electronic Packaging Applications Using Double Cantilever Beam Method,” IEEE Trans. Compon. Packag. Technol., 23(1), pp. 101–116. [CrossRef]
Bao, G. , Ho, S. , Suo, Z. , and Fan, B. , 1992, “ The Role of Material Orthotropy in Fracture Specimens for Composites,” Int. J. Solids Struct., 29(9), pp. 1105–1116. [CrossRef]
Rangaraj, S. , Hicks, J. , O'Day, M. , Aggarwal, A. , Wilson, T. , Panchapakesan, R. , Grover, R. , and Wang, G. , 2013, “ Low-k ILD Reliability Through Chip-Package Assembly: Engineering Appropriate Stress Tests and Process Certification Criteria,” IEEE 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 28–31, pp. 660–666.
Mahan, K. , Kim, B. , Wu, B. , Han, B. , Kim, I. , Moon, H. , and Hwang, Y. N. , 2016, “ Modified Single Cantilever Adhesion Test for EMC/PSR Interface in Thin Semiconductor Packages,” Microelectron. Reliab., 63, pp. 134–141. [CrossRef]
Shin, D. , Lee, J. , Yoon, C. , Lee, G. , Hong, J. , and Kim, N. , 2015, “ Development of Single Cantilever Beam Method to Measure the Adhesion of Thin Film Adhesive on Silicon Chip,” Eng. Fract. Mech., 133, pp. 179–190. [CrossRef]
Kanninen, M. F. , 1973, “ An Augmented Double Cantilever Beam Model for Studying Crack Propagation and Arrest,” Int. J. Fract., 9(1), pp. 83–92.
Rizov, V. , and Mladensky, A. , 2015, “ Elastic–Plastic Analysis of Asymmetric Double Cantilever Beam Specimen,” Int. J. Mech. Sci., 92, pp. 44–51. [CrossRef]
Lim, S. , Chou, J. , Durham, M. , and Mackie, A. , 2015, “ Flux Challenges in Flip-Chip Die-Attach,” IEEE 17th Electronics Packaging and Technology Conference (EPTC), Singapore, Dec. 2–4, pp. 1–5.
Copyright © 2017 by ASME
View article in PDF format.

References

Tong, H. , Lai, Y. , and Wong, C. P. , 2013, Advanced Microelectronic Packaging, Springer, New York.
Sun, P. , Xu, C. , Liu, J. , Geng, F. , and Cao, L. , 2016, “ Flip Chip CSP Assembly With Cu Pillar Bump and Molded Underfill,” 17th International Conference on Electronic Packaging Technology (ICEPT), Wuhan, China, Aug. 16–19, pp. 807–811.
Joshi, M. , Pendse, R. , Pandey, V. , Lee, T. K. , Yoon, I . S. , Yun, J. S. , Kim, Y. C. , and Lee, H. R. , 2010, “ Molded Underfill (MUF) Technology for Flip Chip Packages in Mobile Applications,” 60th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1–4, pp. 1250–1257.
Sinha, T. , Davis, T. J. , Lombardi, T. E. , and Coffin, J. T. , 2015, “ A Systematic Exploration of the Failure Mechanisms in Underfilled Flip-Chip Packages,” IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, May 26–29, pp. 1509–1517.
Paquet, M. C. , Sylvestre, J. , Gros, E. , and Boyer, N. , 2009, “ Underfill Delamination to Chip Sidewall in Advanced Flip Chip Packages,” 59th Electronic Components and Technology Conference (ECTC), San Diego, CA, May 26–29, pp. 960–965.
Lacombe, R. , 2006, Adhesion Measurement Methods: Theory and Practice, CRC Press, Boca Raton, FL.
Pearson, R. , 2014, “ Adhesion Fundamentals for Microelectronic Packaging,” IMAPS 10th International Conference and Exhibition on Device Packaging, Fountain Hills, AZ, Mar. 11–13.
da Silva, L. F. M. , Dillard, D. A. , Blackman, B. R. K. , and Adams, R. D. , 2012, Testing Adhesive Joints, Wiley-VCH, Weinhem, Germany.
Hutchinson, J. W. , and Suo, Z. , 1991, “ Mixed Mode Cracking in Layered Materials,” Adv. Appl. Mech., 29, pp. 63–191.
Li, H. , Kobrinsky, M. J. , Shariq, A. , Richards, J. , Liu, J. and Kuhn, M. , 2013, “ Controlled Fracture of Cu/Ultralow-k Interconnects,” Appl. Phys. Lett., 103(23), p. 231901. [CrossRef]
Dai, X. , Brillhar, M. V. , and Ho, P. S. , 2000, “ Adhesion Measurement for Electronic Packaging Applications Using Double Cantilever Beam Method,” IEEE Trans. Compon. Packag. Technol., 23(1), pp. 101–116. [CrossRef]
Bao, G. , Ho, S. , Suo, Z. , and Fan, B. , 1992, “ The Role of Material Orthotropy in Fracture Specimens for Composites,” Int. J. Solids Struct., 29(9), pp. 1105–1116. [CrossRef]
Rangaraj, S. , Hicks, J. , O'Day, M. , Aggarwal, A. , Wilson, T. , Panchapakesan, R. , Grover, R. , and Wang, G. , 2013, “ Low-k ILD Reliability Through Chip-Package Assembly: Engineering Appropriate Stress Tests and Process Certification Criteria,” IEEE 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 28–31, pp. 660–666.
Mahan, K. , Kim, B. , Wu, B. , Han, B. , Kim, I. , Moon, H. , and Hwang, Y. N. , 2016, “ Modified Single Cantilever Adhesion Test for EMC/PSR Interface in Thin Semiconductor Packages,” Microelectron. Reliab., 63, pp. 134–141. [CrossRef]
Shin, D. , Lee, J. , Yoon, C. , Lee, G. , Hong, J. , and Kim, N. , 2015, “ Development of Single Cantilever Beam Method to Measure the Adhesion of Thin Film Adhesive on Silicon Chip,” Eng. Fract. Mech., 133, pp. 179–190. [CrossRef]
Kanninen, M. F. , 1973, “ An Augmented Double Cantilever Beam Model for Studying Crack Propagation and Arrest,” Int. J. Fract., 9(1), pp. 83–92.
Rizov, V. , and Mladensky, A. , 2015, “ Elastic–Plastic Analysis of Asymmetric Double Cantilever Beam Specimen,” Int. J. Mech. Sci., 92, pp. 44–51. [CrossRef]
Lim, S. , Chou, J. , Durham, M. , and Mackie, A. , 2015, “ Flux Challenges in Flip-Chip Die-Attach,” IEEE 17th Electronics Packaging and Technology Conference (EPTC), Singapore, Dec. 2–4, pp. 1–5.

Figures

Grahic Jump Location
Fig. 1

Schematic cross section of a flip-chip microelectronic package

Grahic Jump Location
Fig. 2

Custom-made fixture allowed CUF to be carefully dispensed in controlled amounts. The fixture was heated so that capillary action aided in uniform CUF dispense.

Grahic Jump Location
Fig. 3

(a) Schematic of the final silicon–CUF DCB sample and (b) side-view of final sample

Grahic Jump Location
Fig. 4

Stack-up of the DCB sample used to measure solder resist–CUF adhesion strength

Grahic Jump Location
Fig. 5

A cross-sectional view of the mold chase showing the solder resist sample being molded

Grahic Jump Location
Fig. 6

Stack-up of the DCB sample used to measure solder resist–EMC adhesion strength

Grahic Jump Location
Fig. 7

(a) Silicon surface with and without roughening and (b) old and new tab designs

Grahic Jump Location
Fig. 8

The DCB chamber concept was an insulating enclosure, with a window to view the sample. The enclosure would fit over the DCB sample, and attach to a heated base plate.

Grahic Jump Location
Fig. 9

(a) A cross section view of the environmental chamber when it is assembled and (b) final assembled environmental chamber wrapped with polyimide insulation and the heater controllers in the background

Grahic Jump Location
Fig. 10

Load–displacement curve from a typical DCB test illustrating the compliance and critical load values

Grahic Jump Location
Fig. 11

Schematic of DCB samples for measuring adhesion strength of uncontaminated and flux contaminated silicon pieces to CUF

Grahic Jump Location
Fig. 12

DCB adhesion strength results comparing the effect of flux contamination on silicon–CUF adhesion

Grahic Jump Location
Fig. 13

Silicon–CUF adhesion strength variation with temperature for CUF B. The results at 25 °C alone were obtained using asymmetric DCB.

Grahic Jump Location
Fig. 14

Silicon–CUF adhesion strength comparison between two CUF materials at three different temperatures. The results at 25 °C alone were obtained using asymmetric DCB.

Grahic Jump Location
Fig. 15

(a) Top down view of DCB fracture surface on silicon side and (b) fracture surface on underfill side

Grahic Jump Location
Fig. 16

Adhesion strength of die passivation materials, DP1 and DP2, to the same CUF material

Grahic Jump Location
Fig. 17

Comparison of solder resist–EMC and solder resist–CUF adhesion strengths using DCB

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In