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Research Papers

Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

[+] Author and Article Information
Herman Oprins

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: oprins@imec.be

Vladimir Cherman

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Vladimir.Cherman@imec.be

Tomas Webers

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Tomas.Webers@imec.be

Abdellah Salahouelhadj

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Abdellah.Salahouelhadj @imec.be

Soon-Wook Kim

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Soon-Wook.Kim@imec.be

Lan Peng

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Lan.Peng@imec.be

Geert Van der Plas

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Geert.Vanderplas@imec.be

Eric Beyne

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: Eric.Beyne@imec.be

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received August 11, 2016; final manuscript received December 12, 2016; published online January 10, 2017. Assoc. Editor: Kaushik Mysore.

J. Electron. Packag 139(1), 011008 (Jan 10, 2017) (9 pages) Paper No: EP-16-1096; doi: 10.1115/1.4035597 History: Received August 11, 2016; Revised December 12, 2016

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

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References

Figures

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Fig. 1

Schematic comparison hybrid Cu/dielectric bonding and dielectric bonding

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Fig. 2

Schematic cross section of the bonded PTCS wafer pair (a). Scanning electron microscope picture of the cross section of the interface of the bonded wafer pair for 3.6 μm pitch (b) and 1.8 μm pitch (c) of the interconnects.

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Fig. 3

Detail of the meander heater element and temperature sensors in the M1 layer of the BEOL

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Fig. 4

Thermal FEM for the thermal test structures in the PTCS test vehicle

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Fig. 5

Temperature measurement of the heaters and sensors in the top and bottom die at the die location (0,0) of the wafer pair

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Fig. 6

Distribution of the power normalized top heater temperature (K/W), measured at different locations on the 300 mm wafer pair

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Fig. 7

Relation between the temperature of the heaters and sensors of the 100 μm structure in the top and bottom wafer and the total die–die thermal resistance

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Fig. 8

Contour plots of the modeling results of the temperature distribution in the thermal test structure

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Fig. 9

Relation between the temperature difference between the top and bottom wafer and the total die–die thermal resistance for the 100 × 100 μm2 and the 200 × 200 μm2 test structures (left). Sensitivity of the extracted die–die thermal resistance to the value of the heat transfer coefficient for the heat losses and the value of the thermal contact resistance between the wafer pair and the probe station, used in the thermal model (right).

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Fig. 10

Distribution of the normalized top—bottom temperature difference (K/W) on the PTCS wafer pair for the 100 μm structure (left) and the 200 μm structure (right)

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Fig. 11

Distribution of the extracted bonded interface thermal resistance (mm2 K/W) on the PTCS wafer pair for the 100 μm structure (left) and the 200 μm structure (right)

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Fig. 12

Fitting of the finite element thermal model to the experimental data of the transient temperature response of the top heater to obtain the bonded interface thermal resistance

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Fig. 13

Steady-state characterization of the quarter wafer pair: normalized temperature difference (a) and extracted intertier thermal resistance (b)

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