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Research Papers

Modeling and Analysis for Thermal Management in Gallium Nitride HEMTs Using Microfluidic Cooling

[+] Author and Article Information
Gunjan Agarwal

Department of Mechanical Engineering,
École polytechnique fédérale de Lausanne,
MED 1 1017 (Batiment MED),
Station 9,
Lausanne 1015, Switzerland
e-mail: agarwalg@alum.mit.edu

Thomas Kazior

Raytheon Integrated Defense Systems,
362 Lowell Street,
Andover, MA 01810
e-mail: Thomas_E_Kazior@raytheon.com

Thomas Kenny

Department of Mechanical Engineering,
Stanford University,
440 Escondido Mall,
Building 530 Room 223,
Stanford, CA 94305
e-mail: kenny@cdr.stanford.edu

Dana Weinstein

Department of Electrical and
Computer Engineering,
Purdue University,
BRK 2266,
465 Northwestern Avenue,
West Lafayette, IN 47907
e-mail: danaw@purdue.edu

1Corresponding authors.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received June 14, 2016; final manuscript received October 25, 2016; published online November 10, 2016. Assoc. Editor: Mehdi Asheghi.

J. Electron. Packag 139(1), 011001 (Nov 10, 2016) (11 pages) Paper No: EP-16-1073; doi: 10.1115/1.4035064 History: Received June 14, 2016; Revised October 25, 2016

In this paper, thermal management in GaN (gallium nitride) based microelectronic devices is addressed using microfluidic cooling. Numerical modeling is done using finite element analysis (FEA), and the results for temperature distribution are presented for a system comprising multiple cooling channels underneath GaN high-electron mobility transistors (HEMTs). The thermal stack modeled is compatible for heterogeneous integration with conventional silicon-based CMOS devices. Parametric studies for cooling performance are done over a range of geometric and flow factors to determine the optimal cooling configuration within the specified constraints. A power dissipation of 2–4 W/mm is modeled along each HEMT finger in the proposed configuration. The cooling arrangements modeled here hold promising potential for implementation in high-performance radio-frequency (RF) systems for power amplifiers, transmission lines, and other applications in defense and military.

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Figures

Grahic Jump Location
Fig. 1

(a) Schematic cross-sectional view of the nominal material stack considered for thermal analysis. Microfluidic cooling channels are etched in a ⟨100⟩ silicon wafer, which is subsequently bonded to a ⟨111⟩ silicon wafer. GaN has a better lattice match to ⟨111⟩ silicon and is subsequently grown as a thin layer on top using molecular beam epitaxy (MBE). (b) Nominal device layout and geometry for a multifinger GaN HEMT (designed by Raytheon Technologies, Andover, MA). The HEMT comprises ten gate fingers, which are 100 μm long and 1 μm wide, pitched at 40 μm apart (center-to-center). There are five drain fingers that are 30 μm wide each, and two source bridges that are 40 μm wide each. (c) Schematic view showing the position and dimensions of the heat sources representative of the multiple GaN HEMT fingers, used for the numerical simulations. (d) Geometry of the 3D model comprising multiple cooling channels underneath a multifinger HEMT (representative of a discrete GaN transistor) when the length of the HEMT fingers (i.e., the direction of gate “width”) is kept parallel to the length of the microfluidic channels and (e) perpendicular to the length of the microfluidic channels. (f) and (g) The FE mesh for the geometries shown in (d) and (e), respectively. The finest mesh elements are used near the fingers where the heat is concentrated.

Grahic Jump Location
Fig. 2

Temperature distribution in the entire material stack upon solving for combined laminar flow and heat transfer problem using FEA in comsol multiphysics for (a) the parallel finger configuration and (b) the perpendicular finger configuration. The dimensions of the material stack are in micrometer, and the temperature values are in degree Celsius. The top views of the stack showing the temperature distribution near the HEMT finger regions are seen for the parallel and perpendicular orientations in (c) and (d), respectively. YZ isothermal plots showing variation of temperature along the depth of the stack, at an X-axis cross section location at the center of the HEMT fingers, are seen in (e) and (f), for the parallel and perpendicular orientations, respectively.

Grahic Jump Location
Fig. 3

Finger–finger variation in temperature with and without cooling for the cases when (a) gate width is kept parallel to the length of the microfluidic channels and (b) gate width is perpendicular to the length of the microfluidic channels. (c) Compares the cooling efficiency of the two design arrangements on the same axes. Much smaller finger–finger temperature variation is observed in the parallel case upon cooling. Temperature variation along the width of the center finger (hottest) is shown in (d) for both the parallel and the perpendicular cases upon cooling. Finger–finger variation in temperature for (e) gate width kept parallel to the length of the microfluidic channels and (f) gate width perpendicular to the length of the microfluidic channels, while varying spacing between heat sources, between 10 and 50 μm. Higher peak temperatures are observed in the thermal stack for tighter finger spacing, for both the cases.

Grahic Jump Location
Fig. 4

Temperature rise along the direction of depth below the hotspot for the cases when (a) gate width is kept parallel to the length of the microfluidic channels and (b) gate width is perpendicular to the length of the microfluidic channels. The ⟨111⟩ silicon layer offers a high thermal resistance. The majority of the temperature drop occurs across the microfluidic channels with effective heat removal from the GaN hotspots.

Grahic Jump Location
Fig. 5

Finger–finger variation in temperature for (a) gate width kept parallel and (b) perpendicular to the length of the microfluidic channels, while varying distance of heat sources from fluid inlets from 100 to 1000 μm. In both the cases, higher peak temperatures are observed for larger distances from fluid inlet. Variation in temperature while varying depth of the cooling microchannels and keeping the flow rate fixed for (c) gate width kept parallel and (d) perpendicular to the length of the microfluidic channels. Variation in temperature while varying the thickness of the ⟨111⟩ silicon layer above the cooling microchannels for (e) gate width kept parallel and (f) perpendicular to the length of the microfluidic channels. The peak temperature in the material stack decreases very slightly with the increase in the thickness of silicon, for both the cases considered.

Grahic Jump Location
Fig. 6

Simulation results for pressure drop obtained at (a) a nominal inlet flow velocity of 1000 mm/s for design 1 for inlet and outlet manifold regions, (b) inlet flow velocity of 5000 mm/s for design 1, (c) nominal inlet flow velocity of 1000 mm/s for design 2 for inlet and outlet manifold regions, and (d) inlet flow velocity of 5000 mm/s for design 2. (e) Peak temperature at any point in the material stack considered, as a function of the Reynolds number for the flow, for both the geometry variations of the gate width parallel as well as perpendicular to the length of the microfluidic channels. The channel width and depth are kept constant at 20 μm, with finger spacing of 30 μm. The rate of drop in peak temperature is observed to be nearly the same for both the cases, regardless of the HEMT orientation. Much lower temperatures are observed in the stack for higher Reynolds number values, corresponding to higher inlet flow rates, resulting in higher cooling efficiency.

Grahic Jump Location
Fig. 7

Simulation results obtained with the adiabatic boundary condition at the base of the ⟨100⟩ silicon substrate and power density of 2 W/mm when (a) gate width is kept parallel and (b) perpendicular to the length of the microfluidic channels, for the nominal cooling system configuration. Finger–finger variation in temperature for (c) gate width kept parallel and (d) perpendicular to the length of the microfluidic channels, while varying spacing between heat sources, between 10 and 50 μm for this case. (e) Peak temperature at any point in the material stack considered, as a function of the Reynolds number for the flow, for both the geometry variations of the gate width parallel as well as perpendicular to the length of the microfluidic channels.

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