Figure 21 shows the placement pitch of CPU-PWBs, lC2,z, versus the total system size, NS. The parameters are the number of on-chip cores, NLB/C0, which is varied from 64 to 1024, and the layout type (A, B). The curves have the labels showing NLB/C0 and the layout type. Large lC2,z means small number of CPU-PWBs in the rack. As noted previously, the increase in the number of on-chip cores is supposed to follow the progress on the technology node scale. Obviously, with the advancement on the technology node, a wider space becomes available in the rack. The effect of layout type on the PWB placement pitch is noteworthy. With NLB/C0 given, the curves for layouts A and B are mutually close in a range of relatively small system size NS. With increasing NS, layout B yields an obvious advantage over layout A in relaxing the spatial condition in the rack (increasing lC2,z). That is, concentration of L-cells to dedicated PWBs and accommodation of M2-cells in separate PWBs is a way to reduce the total number of PWBs in the rack. The advantage of layout B over A comes largely from the increased cell accommodation capacity of memory PWBs. That is, the level-2 memory chips (MC2-cards) are mounted on two sides of the PWB. Where the logic processing components (MCMs) are present, use of the two sides of PWB to mount components is generally difficult. This is because the PWB with MCMs has to accommodate complex wirings in high routing density, and two-side mounting of memory chips further complicates wiring in PWB, an economically and technically unfavorable option.