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Research Papers

Review on Percolating and Neck-Based Underfills for Three-Dimensional Chip Stacks

[+] Author and Article Information
Thomas Brunschwiler

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: tbr@zurich.ibm.com

Jonas Zürcher

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: zur@zurich.ibm.com

Luca Del Carro

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: ldc@zurich.ibm.com

Gerd Schlottig

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: erd@zurich.ibm.com

Brian Burg

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: bbu@zurich.ibm.com

Severin Zimmermann

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: sev@zurich.ibm.com

Uwe Zschenderlein

Department of Materials and
Reliability of Microsystems,
Technical University of Chemnitz,
Reichenhainer Street 70,
Chemnitz 09126, Germany
e-mail: uwe.zschenderlein@etit.tu-chemnitz.de

Bernhard Wunderle

Department of Materials and
Reliability of Microsystems,
Technical University of Chemnitz,
Reichenhainer Street 70,
Chemnitz 09126, Germany
e-mail: bernhard.wunderle@etit.tu-chemnitz.de

Florian Schindler-Saefkow

AMIC—Angewandte Micro-Messtechnik GmbH,
Säumerstrasse 4,
Volmerstraße 9,
Berlin 12489, Germany
e-mail: florian.schindler-saefkow@amic-berlin.de

Rahel Stässle

IBM Research—Zurich,
Säumerstrasse 4,
Rüschlikon 8803, Switzerland
e-mail: rah@zurich.ibm.com

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 25, 2016; final manuscript received October 6, 2016; published online October 21, 2016. Assoc. Editor: Ashish Gupta.

J. Electron. Packag 138(4), 041009 (Oct 21, 2016) (10 pages) Paper No: EP-16-1090; doi: 10.1115/1.4034927 History: Received July 25, 2016; Revised October 06, 2016

Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.

Copyright © 2016 by ASME
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References

Figures

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Fig. 1

Sequential process to achieve neck-based percolating thermal underfills in three main steps: (1) Formation of percolating filler particle bed by centrifugation. (2) Formation of enhanced particle-to-particle contacts, so-called necks. (3) Backfilling of the open porous structure by an unfilled adhesive using capillary action. (The filling of multiple cavities of a chip stack is analogous.)

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Fig. 2

Size distribution of the raw DAW-07 alumina particles and the refined FP-05 particles derived by the sedimentation process

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Fig. 3

Viscosity of the MM-2 matrix material as a function of temperature

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Fig. 4

Photograph of (a) the silicon-glass test cavity (TC) and (b) the microprocessor demonstrator module (MDM). (c) SEM image of the silicon pillars of the microprocessor test vehicle (MTV) representing the solder ball array of the MDM.

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Fig. 5

Isometric view of the rotating disk with a capacity of four modules. The cover plate contains the central feed and the guiding structures to direct the filler particles toward the modules.

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Fig. 6

Schematic view of the filler-particle dispensing and filling process using a centrifugal disk and a syphon feed

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Fig. 7

(a) Illustration of the neck-formation processes using directed self-assembly by capillary bridging. The evaporation front drives nanoparticles into the contact area between micron-sized filler particles. (b) Scanning electron microscope (SEM) image showing the necks formed between percolating filler particles in the cavity and between the filler particles and the chip surface.

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Fig. 8

Microscopic views through the cover glass plate of the TC showing the evolution of capillary bridges during the evaporation of water at 60 °C. Two different evaporation patterns that occur in sequence were identified: (1) dendritic network growth (left), and (2) collapse of capillary bridges (right) (evaporation front: dashed line in the local close-ups (c,d)).

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Fig. 9

SEM images of neck morphologies assembled from (a) NP-40 between microsilica, (b) NP-250 between microsilica, and (c) a mixture of NP-40 and NP-250 between micro-alumina (FP-34)

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Fig. 10

Photographs of the epoxy flow-front evolution (a) at t1 and (b) at t2 (t1 < t2) for high-dispensing rates, resulting in a rapid progression of the viscous material along the chip edge and entrapment of air in the center

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Fig. 11

Photographs of (a) the TC during back-filling, showing the instable fill front and air inclusions, and (b) the MTV filled with FP-05, backfilled with MM-2, and cured by the over-pressure process

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Fig. 12

Micrograph through the MTV glass lid depicting the FP-05 filler-particle arrangement around a silicon pillar for (a) dry filling and (b) wet filling. The arrow indicates the feed direction and the red oval indicates a shadowing location. (c) SEM image of FP-05 assembled in a TC.

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Fig. 13

SEM image of an NTU cross section (a) with necks formed between FP-34 filler particles by a mixture of NP-40 and NP-250. (b) Close-up of a single neck between two alumina filler particles shows the homogeneous distribution of nanoparticles. The epoxy matrix did not penetrate into the neck pores.

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Fig. 14

Underfill thermal conductivity derived from TC specimens with 60 μm underfill thickness. The CTU is compared with underfill sets prepared with MM-1 or MM-2 matrix material. Within each set, the matrix material only, the percolating thermal underfill (PTU), and the neck-based thermal underfills (NTU) are compared.

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Fig. 15

First principal stress in the analyzed corner solder-joint after a third thermal cycle, showing all three different underfills. Bottom line: (a) schematic of the entire model wedge, (b) cut corner zone, and (c) detail showing the solder joint and next to it the underfill modeled as effective layer.

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Fig. 16

Simulation results for the three different underfills, as well as the PTU with an unfilled epoxy fillet. Top-to-bottom: first principal stress in the die, radial shear stress in the underfill-to-die interface, accumulated equivalent creep strain normalized to CMU, shear and normal (opening) stresses of the top fillet edge to die, and of the bottom fillet edge to substrate.

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Fig. 17

Scanning ultrasound image of the PTU-filled MDM after processing. The scale indicates the amplitude of the reflected signal at the chip-to-underfill interface. A negative amplitude suggests an interface from a material with a higher impedance to one with a lower impedance.

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Fig. 18

SEM cross section of the two-die chip stack, filled with PTU (FP-05) and MCU within the chip stack and between bottom die and laminate, respectively

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Fig. 19

Thermal performance benchmark for the various underfill solutions and chip stacks with varying die numbers relative to the maximal heat flux of the commercially available CTU. The effective interconnect thermal resistance (solder and underfill) for the benchmark materials are also shown.

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