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Research Papers

Optimal Shock Pulse in a Drop Test Simulation of Standardized Board for Uniform Shock Response

[+] Author and Article Information
Sharan Kallolimath

Department of Mechanical Engineering,
Lamar University,
4400 MLK Drive,
Beaumont, TX 77705
e-mail: sckallolima@lamar.edu

Jiang Jenny Zhou

Professor
Department of Mechanical Engineering,
Lamar University,
4400 MLK Drive,
Beaumont, TX 77705
e-mail: jenny.zhou@lamar.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received September 29, 2014; final manuscript received July 14, 2016; published online August 10, 2016. Assoc. Editor: Toru Ikeda.

J. Electron. Packag 138(4), 041001 (Aug 10, 2016) (10 pages) Paper No: EP-14-1082; doi: 10.1115/1.4034187 History: Received September 29, 2014; Revised July 14, 2016

Board-level physical test performance of CSP/BGA packages need in depth characterization of loading parameters and material behavioral properties. In recent years, many calibration methods were adopted by the researchers and industries to improvise solder joint performances of packages. Effective and uniform board response is one of the critical challenges in developing test board to qualify package components for solder joint reliability qualification. In this paper, an improvised board type alternative to standard Joint Electron Device Engineering Council (JEDEC) board is developed for uniform stress/strain response. An axis symmetrical board is chosen in comparison to the current JEDEC board. The effectiveness of the two boards are compared with each other under extreme banding under controlled drop test simulation. The uniform stress–stain distribution is recorded maintaining the no-ring phenomenon by selecting optimal shock pulse parameters. Selected impact/shock pulse is decided by identifying the maximum impact energy absorbed by the board during the drop event. Board surface strain and stress data are captured 1–2 mm away near the components are quantified for higher strain rate. The board local strain rate on the board surface is recorded at a selected time-step to quantify the dynamic stresses along the component side surface on the board. The simulation is performed by using ANSYS software using implicit method. Both linear SOLID45 and quadratic SOLID95 elements are used to compare and correlate the results. Close forms of results were correlated with the previous theoretical results.

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References

Lall, P. , Shantaram, S. , Suhling, J. , and Locker, D. , 2015, “ Stress–Strain Behavior of SAC305 at High Strain Rates,” ASME J. Electron. Packag., 137(1), p. 011010. [CrossRef]
Ranouta, A. S. , Fan, X. J. , and Han, Q. , 2009, “ Shock Performance Study of Solder Joints in Wafer Level Packages,” International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP '09), Beijing, China, Aug. 10–13, pp. 1266–1276.
JEDEC, 2003, “ Board Level Drop Test Method of Components for Handheld Electronic Products,” JEDEC, Arlington, VA, Standard No. JESD22-B111.
Suhir, E. , 1994, “ Dynamic Response of a Rectangular Plate to a Shock Load, With Application to Portable Electronic Product,” IEEE Trans. Compon., Packag., Manuf. Technol., 17(3), pp. 449–460. [CrossRef]
Suhir, E. , 1997, “ Is the Maximum Acceleration an Adequate Criterion of the Dynamic Strength of a Structural Element in an Electronic Product?” IEEE Trans. Compon., Packag., Manuf. Technol., 20(4), pp. 513–517. [CrossRef]
Dhiman, H. , Fan, X. , and Zhou, T. , 2009, “ JEDEC Board-Drop Test Simulation for Wafer Level Packages (WLPs),” IEEE 59th Electronic Components and Technology Conference (ECTC 2009), San Diego, CA, May 26–29, pp. 556–564.
Zhou, J. , Niraula, R. P. , and Aung, K. T. , 2007, “ Analysis on the Effect of Input Profiles in Drop Test,” ASME Paper No. IMECE2007-41138.
Human, H. S. , Fan, X. , and Zhou, T. , 2008, “ Modeling Techniques for Board Level Drop Test for a Wafer-Level Package,” International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP 2008), Shanghai, July 28–31.
Xi, J. , Zhai, X. , Wang, J. , Yang, D. , Ru, M. , Xiao, F. , Zhang, L. , Lai, C. M. , 2015, “ Reliability Assessment of Wafer Level Packages with Novel FeNi Under Bump Metallization,” ASME J. Electron. Packag., 137(3), p. 031016. [CrossRef]
Zhou, J. , 2008, “ Analytical Analysis on the Effect of Time Duration of Acceleration Pulse to a JEDEC Board in Drop Test,” International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP 2008), Shanghai, July 28–31.
Tee, T. Y. , Luan, J.-e. , Pek, E. , Lim, C. T. , and Zhong, Z. , 2004, “ Dynamic Responses Under Board Level Drop Test,” 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2004), Brussels, Belgium, May 10–12.
Tee, T. Y. , Luan, J. E. , Pek, E. , Lim, C. T. , and Zhong, Z. W. , 2004, “ Novel Numerical and Experimental Analysis of Dynamic Responses Under Board Level Drop Test,” 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2004), Brussels, Belgium, May 10–12, pp. 133–140.
Luan, J. E. , and Tee, T. Y. , 2004, “ Novel Board Level Drop Test Simulation Using Implicit Transient Analysis With Input-G Method,” 6th Electronics Packaging Technology Conference (EPTC 2004), Singapore, Dec. 8–10, pp. 671–677.
Suhir, E. , 2002, “ Could Shock Tests Adequately Replace Drop Tests,” 8th International Symposium of Advance Packaging, (ISAPM), Stone Mountain, GA, Mar. 3–6, pp. 67–81.
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Figures

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Fig. 3

JEDEC board displacement due to typical one-half sine impact acceleration

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Fig. 4

Initial stress waves on the components: block diagram of drop test system [3]

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Fig. 5

Forcing functions: (a) one-half sine [3], (b) one-half sine squared, (c) trapezoid, [2], and (d) trapezoid pulses

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Fig. 8

Comparative mode shapes and fundamental frequencies

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Fig. 9

Boundary conditions of Hex model and JEDEC standard model (quarter model): (a) JEDEC standard model and (b) Hex model

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Fig. 10

Global modal displacements at constrained modal frequency: (a) JEDEC board displacement and (b) Hex board displacement

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Fig. 11

No-ring board displacement response at the center of the boards

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Fig. 12

No-ring board acceleration response at the center of the boards

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Fig. 13

Board surface strain during first half of sine impact pulse on standard JEDEC test board vehicle

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Fig. 14

Principal Strain along X3 path at given time-step for standard JEDEC board dimension

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Fig. 15

Principal strain along X2 path at given time-step for standard JEDEC board dimension

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Fig. 17

Principal strain along path-A at given time-step for new hexagonal board dimension

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Fig. 18

Principal strains along on selected strain path in JEDEC board: (a) principal strain—SOLID45 (linear) and (b) principal strain—SOLID95 (quadratic)

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Fig. 19

Principal strains along on selected strain path in hexagonal board

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Fig. 20

Principal stress variations of JEDEC and Hex board: (a) JEDEC board stresses and (b) Hex board stresses

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Fig. 21

Maximum von Mises stresses near standoffs

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Fig. 16

Principal strain along path-A at given time-step for new hexagonal board dimension

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Fig. 7

Comparative model areas and strain regions and path: (a) new board vehicle and (b) standard JEDEC board

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Fig. 6

Displacement response of continuous beam system

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Fig. 2

Half sine impact pulse profile with duration τ and the magnitude Gp, from JEDEC standard drop tester [3]

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Fig. 1

Layout of the JEDEC test board [1]

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