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Research Papers

Embedded Two-Phase Cooling of Large Three-Dimensional Compatible Chips With Radial Channels

[+] Author and Article Information
Mark Schultz

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: markds@us.ibm.com

Fanghao Yang

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: yangf@us.ibm.com

Evan Colgan

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: ecolgan@us.ibm.com

Robert Polastre

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: polastr@us.ibm.com

Bing Dang

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: dangbing@us.ibm.com

Cornelia Tsang

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: cornelia@alum.mit.edu

Michael Gaynes

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: ganyesma@us.ibm.com

Pritish Parida

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: prparida@us.ibm.com

John Knickerbocker

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: knickerj@us.ibm.com

Timothy Chainer

IBM T. J. Watson Research Center,
1101 Kitchawan Road,
Yorktown Heights, NY 10598
e-mail: tchainer@us.ibm.com

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received September 14, 2015; final manuscript received March 14, 2016; published online April 25, 2016. Assoc. Editor: Mehdi Asheghi.

J. Electron. Packag 138(2), 021005 (Apr 25, 2016) (5 pages) Paper No: EP-15-1084; doi: 10.1115/1.4033309 History: Received September 14, 2015; Revised March 14, 2016

Thermal performance for embedded two-phase cooling using dielectric coolant (R1234ze) is evaluated on a ∼20 mm × 20 mm large die. The test vehicles incorporate radial expanding channels with embedded pin fields suitable for through-silicon-via (TSV) interconnects of multidie stacks. Power generating features mimicking those anticipated in future generations of processor chips with eight cores are included. Initial results show that for the types of power maps anticipated, critical heat fluxes (CHFs) in “core” areas of at least 350 W/cm2 with at least 20 W/cm2 “background” heating in rest of the chip area can be achieved with less than 30 °C temperature rise over the inlet coolant temperature. These heat fluxes are significantly higher than those seen for relatively long parallel channel devices of similar base channel dimensions. Experimental results of flow rate, pressure drop, “device,” and coolant temperature are also provided for these test vehicles along with details of the test facility developed to properly characterize the test vehicles.

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References

Figures

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Fig. 1

Basic heater layout of the TTV

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Fig. 2

Detailed heater layout of the TTV. Numbered sensor locations are also shown.

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Fig. 3

Coolant channel and pin layout for TTV

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Fig. 5

Test system diagram

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Fig. 6

Single-phase pressure drop versus flow rate

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Fig. 7

Interpolated temperature map

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Fig. 8

Average core temperature rise and thermal resistance versus core input heat flux (15 kg/hr mass flow)

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Fig. 9

Twelve core sensor junction temperatures (15 kg/hr mass flow). Legend gives sensor number of Fig. 2.

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Fig. 10

Inlet absolute pressure and pressure drop across TTV versus heat flux for two-powered quadrants (15 kg/hr mass flow)

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