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Research Papers

Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations

[+] Author and Article Information
M. Baris Dogruoz

Cisco Systems, Inc.,
San Jose, CA 95134
e-mail: dogruozb2@asme.org

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 19, 2016; final manuscript received March 18, 2016; published online April 19, 2016. Assoc. Editor: Mehmet Arik.

J. Electron. Packag 138(2), 021004 (Apr 19, 2016) (8 pages) Paper No: EP-16-1035; doi: 10.1115/1.4033109 History: Received February 19, 2016; Revised March 18, 2016

A printed circuit board (PCB) comprises a solid piece of dielectric material with embedded layers of current carrying metal traces and vias. Geometric features of these metal traces and vias in modern PCBs are highly nonuniform and complicated such that the card level or system level numerical simulations by using the actual trace and via geometries are computationally expensive. The present study investigates the effects of Joule heating in current carrying traces on the temperature distribution of PCBs by conducting one-way and two-way direct current (DC) electric and computational fluid dynamics (CFD) simulations. DC electric field simulations are performed to determine the power map of trace layers which are modeled as planar heat generating sources by using the temperature-dependent electrical conductivity of the metal trace. The power distribution varies with the implemented size and power thresholds. Thermal conductivity map of the PCB is determined by using the electronic computer-aided design (ECAD) images of the individual layers. By using these planar source and thermal conductivity maps, CFD simulations are conducted to determine the resulting temperature distribution on the board. A methodology is developed and applied to a sample, complex PCB, and the generated results are compared with those of the previous studies and conventional models. The computational data show that the temperature distributions over the PCB and its mounted components experience large variations based on the implemented thermal conductivity mapping and the Joule heating modeling technique.

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Figures

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Fig. 1

A complex PCB design

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Fig. 2

Flowchart showing the computational methodology

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Fig. 3

CFD model (H: high (top) side and L: low (bottom) side of the PCB)

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Fig. 4

Model validation—symbols: experiments [32] and solid line: present computations

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Fig. 5

Current density vectors (j) in the top trace layer: (a) PCB top surface and (b) zoom-in to the via array on the “NVDD” trace

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Fig. 6

Two-way simulations (case 6) with 5 mW/0.127 mm (power/size) filters. Top—Joule heating power map (left) and temperature distribution (right) for the top layer. Bottom—Joule heating power map (left) and temperature distribution (right) for the bottom layer. Lines (plots on the left)—Bold: top surface components, medium: bottom surface components, light: sources in the layers. There are a total of 638 sources on the top layer, 204 sources on the bottom layer, and 1072 sources on the PCB.

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Fig. 7

Thermal conductivity distribution in normal direction, κt,: top layer (top) and bottom layer (bottom)

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Fig. 8

Detailed versus lumped thermal conductivity—individual component temperature values of cases 1 and 2, with qJ = 0

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Fig. 9

Effects of Joule heating on individual component temperature values—cases 2 and 4

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Fig. 10

Effects of Joule heating modeling on individual component temperature values—cases 4–6

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Fig. 11

Lumped versus fully detailed model—individual component temperature values of cases 3 and 6

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Fig. 12

Distribution of DR values for cases 2, 4, and 5

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