Research Papers

Three-Dimensional Integrated Circuit With Embedded Microfluidic Cooling: Technology, Thermal Performance, and Electrical Implications

[+] Author and Article Information
Xuchen Zhang

School of Electrical and Computer Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332
e-mail: xzhang96@gatech.edu

Xuefei Han, Craig E. Green, Peter A. Kottke, Andrei G. Fedorov, Yogendra Joshi

G. W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332

Thomas E. Sarvey, Muhannad S. Bakir

School of Electrical and Computer Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received October 2, 2015; final manuscript received January 3, 2016; published online March 10, 2016. Assoc. Editor: Jeffrey C. Suhling.

J. Electron. Packag 138(1), 010910 (Mar 10, 2016) (9 pages) Paper No: EP-15-1107; doi: 10.1115/1.4032496 History: Received October 02, 2015; Revised January 03, 2016

This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 μm and pin diameters of 90 μm and 30 μm. Single-phase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm2 to 470 W/cm2. The maximum heat transfer coefficient reached was 60 kW/m2 K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design.

Copyright © 2016 by ASME
Your Session has timed out. Please sign back in to continue.



Grahic Jump Location
Fig. 1

Schematic of 3D IC with microfluidic cooling

Grahic Jump Location
Fig. 2

Optical and scanning electron microscopy image of the heat sink

Grahic Jump Location
Fig. 3

Fabrication process of the heat sink sample

Grahic Jump Location
Fig. 4

Flow loop schematic

Grahic Jump Location
Fig. 5

Pin-fin array dimensions

Grahic Jump Location
Fig. 6

(a) Heat transfer coefficient, (b) mean temperature difference from wall to fluid, (c) convective resistance, and (d)pressure drop for single-phase

Grahic Jump Location
Fig. 7

(a) Local two-phase heat transfer coefficient, (b) boiling curve, (c) pressure drop, and (d) vapor quality

Grahic Jump Location
Fig. 8

Flow visualization of sample 1 at 381 W

Grahic Jump Location
Fig. 9

Three-dimensional interconnect link

Grahic Jump Location
Fig. 10

Delay, wire length, and TSV capacitance versus (a) micropin-fin pitch and (b) TSV height

Grahic Jump Location
Fig. 11

Delay and RCONV versus (a) micropin-fin pitch and (b) TSV height




Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In