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Research Papers

Three-Dimensional Integrated Circuit With Embedded Microfluidic Cooling: Technology, Thermal Performance, and Electrical Implications

[+] Author and Article Information
Xuchen Zhang

School of Electrical and Computer Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332
e-mail: xzhang96@gatech.edu

Xuefei Han, Craig E. Green, Peter A. Kottke, Andrei G. Fedorov, Yogendra Joshi

G. W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332

Thomas E. Sarvey, Muhannad S. Bakir

School of Electrical and Computer Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received October 2, 2015; final manuscript received January 3, 2016; published online March 10, 2016. Assoc. Editor: Jeffrey C. Suhling.

J. Electron. Packag 138(1), 010910 (Mar 10, 2016) (9 pages) Paper No: EP-15-1107; doi: 10.1115/1.4032496 History: Received October 02, 2015; Revised January 03, 2016

This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 μm and pin diameters of 90 μm and 30 μm. Single-phase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm2 to 470 W/cm2. The maximum heat transfer coefficient reached was 60 kW/m2 K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design.

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References

Jeddeloh, J. , and Keeth, B. , 2012, “ Hybrid Memory Cube New DRAM Architecture Increases Density and Performance,” 2012 IEEE Symposium on VLSI Technology (VLSIT), Honolulu, HI, June 12–14, pp. 87–88.
Meindl, J. D. , 2003, “ Interconnect Opportunities for Gigascale Integration,” IEEE Micro, 23(3), pp. 28–35. [CrossRef]
Bohr, M. T. , 1995, “ Interconnect Scaling—The Real Limiter to High Performance ULSI,” International Electron Devices Meeting (IEDM’95), Washington, DC, Dec. 10–13, pp. 241–244.
Lau, J. H. , 2014, “ Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration,” ASME J. Electron. Packag., 136(4), p. 040801. [CrossRef]
Zhang, Y. , Zheng, L. , and Bakir, M. S. , 2013, “ 3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs,” IEEE Trans. CPMT, 3(11), pp. 1811–1819.
Sarvey, T. E. , Zhang, Y. , Zhang, Y. , Oh, H. , and Bakir, M. S. , 2014, “ Thermal and Electrical Effects of Staggered Micropin-Fin Dimensions for Cooling of 3D Microsystems,” 2014 IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, FL, May 27–30, pp. 205–212.
Madhour, Y. , d'Entremont, B. P. , Marcinichen, J. B. , Michel, B. , and Thome, J. R. , 2014, “ Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks,” ASME J. Electron. Packag., 136(2), p. 021006. [CrossRef]
Zhang, Y. , Dembla, A. , Joshi, Y. , and Bakir, M. S. , 2012, “ 3D Stacked Microfluidic Cooling for High-Performance 3D ICs,” IEEE 62nd Electronic Components and Technology Conference (ECTC 2012), San Diego, CA, May 29–June 1, pp. 1644–1650.
Tuckerman, D. B. , and Pease, R. F. W. , 1981, “ High-Performance Heat Sinking for VLSI,” IEEE Electron. Device Lett., 2(5), pp. 126–129. [CrossRef]
Brunschwiler, T. , Paredes, S. , Drechsler, U. , Michel, B. , Cesar, W. , Toral, G. , Temiz, Y. , and Leblebici, Y. , 2009, “ Validation of the Porous-Medium Approach to Model Interlayer-Cooled 3D-Chip Stacks,” IEEE International Conference on 3D System Integration (3DIC 2009), San Francisco, CA, Sept. 28–30, pp. 1–10.
Peles, Y. , Kosar, A. , Mishra, C. , Kuo, C. J. , and Schneider, B. , 2005, “ Forced Convective Heat Transfer Across a Pin Fin Micro Heat Sink,” Int. J. Heat Mass Transfer, 48(17), pp. 3615–3627. [CrossRef]
Qu, W. , and Siu-Ho, A. , 2008, “ Experimental Study of Saturated Flow Boiling Heat Transfer in an Array of Staggered Micro-Pin-Fins,” Int. J. Heat Mass Transfer, 52(7–8), pp. 1853–1863.
Reeser, A. , Bar-Cohen, A. , and Hetsroni, G. , 2014, “ High Quality Flow Boiling Heat Transfer and Pressure Drop in Microgap Pin Fin Arrays,” Int. J. Heat Mass Transfer, 78, pp. 974–985. [CrossRef]
Koşar, A. , and Peles, Y. , 2007, “ Boiling Heat Transfer in a Hydrofoil-Based Micro Pin Fin Heat Sink,” Int. J. Heat Mass Transfer, 50(5–6), pp. 1018–1034. [CrossRef]
Krishnamurthy, S. , and Peles, Y. , 2008, “ Flow Boiling of Water in a Circular Staggered Micro-Pin Fin Heat Sink,” Int. J. Heat Mass Transfer, 51(5–6), pp. 1349–1364. [CrossRef]
Tullius, J. F. , Tullius, T. K. , and Bayazitoglu, Y. , 2012, “ Optimization of Short Micro Pin Fins in Minichannels,” Int. J. Heat Mass Transfer, 55(15–16), pp. 3921–3932. [CrossRef]
Rubinstein, J. , Penfield, P. , and Horowitz, M. A. , 1983, “ Signal Delay in RC Tree Networks,” IEEE Trans. Comput. Aided Des., 2(3), pp. 202–211. [CrossRef]
Sarafis, P. , Benech, P. , and Nassiopoulou, A. G. , 2014, “ Cu Nanolines for Application in RF Interconnect,” 15th International Conference on Ultimate Integration on Silicon (ULIS), Stockholm, Sweden, Apr. 7–9, pp. 149–152.

Figures

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Fig. 1

Schematic of 3D IC with microfluidic cooling

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Fig. 2

Optical and scanning electron microscopy image of the heat sink

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Fig. 3

Fabrication process of the heat sink sample

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Fig. 4

Flow loop schematic

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Fig. 5

Pin-fin array dimensions

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Fig. 6

(a) Heat transfer coefficient, (b) mean temperature difference from wall to fluid, (c) convective resistance, and (d)pressure drop for single-phase

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Fig. 7

(a) Local two-phase heat transfer coefficient, (b) boiling curve, (c) pressure drop, and (d) vapor quality

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Fig. 8

Flow visualization of sample 1 at 381 W

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Fig. 9

Three-dimensional interconnect link

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Fig. 10

Delay, wire length, and TSV capacitance versus (a) micropin-fin pitch and (b) TSV height

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Fig. 11

Delay and RCONV versus (a) micropin-fin pitch and (b) TSV height

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