0
Research Papers

Modeling Thermal Microspreading Resistance in Via Arrays

[+] Author and Article Information
Michael Fish

Department of Mechanical Engineering,
Clark School of Engineering,
University of Maryland,
College Park, MD 20742
e-mail: mcfish@umd.edu

Patrick McCluskey

Department of Mechanical Engineering,
Clark School of Engineering,
University of Maryland,
College Park, MD 20742
e-mail: mcclupa@umd.edu

Avram Bar-Cohen

Department of Mechanical Engineering,
Clark School of Engineering,
University of Maryland,
College Park, MD 20742
e-mail: abc@umd.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received September 25, 2015; final manuscript received December 17, 2015; published online March 11, 2016. Assoc. Editor: Xiaobing Luo.The United States Government retains, and by accepting the article for publication, the publisher acknowledges that the United States Government retains, a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this work, or allow others to do so, for United States Government purposes.

J. Electron. Packag 138(1), 010909 (Mar 11, 2016) (9 pages) Paper No: EP-15-1097; doi: 10.1115/1.4032348 History: Received September 25, 2015; Revised December 17, 2015

As thermal management techniques for three-dimensional (3D) chip stacks and other high-power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased. To reduce the computational costs and time in the thermal analysis of through-layer via (TXV) structures, much research to date has focused on defining effective anisotropic thermal properties for a pseudohomogeneous medium using isothermal boundary conditions. While such an approach eliminates the need to model heat flow through individual vias, the resulting properties are found to depend on the specific boundary conditions applied to a unit TXV cell. More specifically, effective properties based on isothermal boundary conditions fail to capture the local “microspreading” resistance associated with more realistic heat flux distributions and local hot spots on the surface of these substrates. This work assesses how the thermal microspreading resistance present in arrays of vias in interposers, substrates, and other package components can be properly incorporated into the modeling of these arrays. We present the conditions under which spreading resistance plays a major role in determining the thermal characteristics of a via array and propose methods by which designers can both account for the effects of microspreading resistance and mitigate its contribution to the overall thermal behavior of such substrate–via systems. Finite element modeling (FEM) of TXV unit cells is performed using commercial simulation software (ansys).

FIGURES IN THIS ARTICLE
<>
Copyright © 2016 by ASME
Your Session has timed out. Please sign back in to continue.

References

Lau, J. H. , 2014, “ Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration,” ASME J. Electron. Packag., 136(4), p. 040801. [CrossRef]
Goplen, B. , and Sapatnekar, S. S. , 2006, “ Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 25(4), pp. 692–708. [CrossRef]
Cong, J. , Luo, G. , and Shi, Y. , 2011, “ Thermal-Aware Cell and Through-Silicon-Via Co-Placement for 3D ICs,” 48th ACM/EDAC/IEEE Design Automation Conference (DAC 2011), New York, June 5–9, pp. 670–675.
Said, M. , Mehdipour, F. , and El-Sayed, M. , 2013, “ Thermal Analysis of Three-Dimensional ICs, Investigating the Effect of Through-Silicon Vias and Fabrication Parameters,” 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, (EDAPS 2013), Nara, Japan, Dec. 12–15, pp. 165–168.
Wong, E. , and Lim, S. K. , 2006, “ 3D Floorplanning With Thermal Vias,” Design, Automation and Test in Europe, (DATE’06), Munich, Germany, Mar. 6–10.
Cho, S. , Joshi, Y. , Sundaram, V. , Sato, Y. , and Tummala, R. , 2013, “ Comparison of Thermal Performance Between Glass and Silicon Interposers,” 63rd IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 28–31, pp. 1480–1487.
Cho, S. , Sundaram, V. , Tummala, R. R. , and Joshi, Y. K. , 2015, “ Impact of Copper Through-Package Vias on Thermal Performance of Glass Interposers,” IEEE Trans. Compon., Packag., Manuf. Technol., 5(8), pp. 1075–1084. [CrossRef]
Chien, H.-C. , Lau, J. H. , Chao, Y.-L. , Dai, M.-J. , Tain, R.-M. , Li, L. , Su, P. , Xue, J. , and Brillhart, M. , 2012, “ Thermal Evaluation and Analyses of 3D IC Integration SiP With TSVs for Network System Applications,” 62nd IEEE Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29–June 1, pp. 1866–1873.
Liu, Z. , Swarup, S. , and Tan, S. X.-D. , 2013, “ Compact Lateral Thermal Resistance Modeling and Characterization for TSV and TSV Array,” 32nd IEEE/ACM International Conference on Computer-Aided Design, (ICCAD 2013), San Jose, CA, Nov. 18–21, pp. 275–280.
Lee, S. , Lemczyk, T. F. , and Yovanovich, M. M. , 1992, “ Analysis of Thermal Vias in High Density Interconnect Technology,” 8th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, (SEMI-THERM) VIII, Austin, TX, Feb. 3–5, pp. 55–61.
Xu, H. , Pavlidis, V. F. , and De Micheli, G. , 2011, “ Analytical Heat Transfer Model for Thermal Through-Silicon Vias,” 14th Design, Automation and Test in Europe Conference and Exhibition, (DATE 2011), Grenoble, France, Mar. 14–18, pp. 395–400.
Santos, C. , Momar Souare, P. , and de Crecy, F. , 2014, “ Using TSVs for Thermal Mitigation in 3D Circuits: Wish and Truth,” International 3D Systems Integration Conference (3DIC), Kinsdale, Ireland, Dec. 1–3, pp. 1–8.
Chen, Z. , Luo, X. , and Liu, S. , 2010, “ Thermal Analysis of 3D Packaging With a Simplified Thermal Resistance Network Model and Finite Element Simulation,” 11th International Conference on Electronic Packaging Technology and High Density Packaging, (ICEPT-HDP), Xi'an, China, Aug. 16–19, Association for Computing Machinery, pp. 737–741.
Li, R. S. , 1998, “ Optimization of Thermal Via Design Parameters Based on an Analytical Thermal Resistance Model,” 6th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, (ITHERM'98), Seattle, WA, May 27–30, pp. 475–480.
Yovanovich, M. M. , Culham, J. R. , and Teertstra, P. , 1998, “ Analytical Modeling of Spreading Resistance in Flux Tubes, Half Spaces, and Compound Disks,” IEEE Trans. Compon., Packag., Manuf. Technol., Part A, 21(1), pp. 168–176. [CrossRef]
Bar-Cohen, A. , 2013, Encyclopedia of Thermal Packaging. Set 1: Thermal Packaging Techniques, World Scientific Publishing, Singapore, p. 359.
Takahashi, S. , Horiuchi, K. , and Tatsukoshi, K. , 2013, “ Development of Through Glass Via (TGV) Formation Technology Using Electrical Discharging for 2.5/3D Integrated Packaging,” 63rd IEEE Electronic Components and Technology Conference, (ECTC 2013), Las Vegas, NV, May 28–31, pp. 348–352.

Figures

Grahic Jump Location
Fig. 1

Via unit cells. From left to right: (a) TSV cell as used in Ref. [8], showing the many features that can appear in a TXV array, (b) Cu–glass via cell used to investigate boundary conditions, and (c) Cu–glass cell for investigating the contribution of films

Grahic Jump Location
Fig. 2

Heat flux vectors at a vertical cross section of a unit cell. The top and bottom faces of the cell have constant flux boundary conditions of the same magnitude. The midplane contains an isotherm, as evidenced by the parallel flux vectors there. Units are in W/m2.

Grahic Jump Location
Fig. 3

Unit cell for investigating convection boundary condition. The lateral dimensions and materials are held constant, while the top boundary condition and substrate thickness are varied. Due to symmetry, a quarter-cell is modeled in practice.

Grahic Jump Location
Fig. 4

Dependence of keff,z on substrate thickness and applied heat transfer coefficient

Grahic Jump Location
Fig. 5

Via cell total thermal resistance, calculated from FEM. Related to keff,z data presented in Fig. 4 by Eq. (7). Cells in the “thick substrate” regime have converged to a linear asymptote unique to each h. Three high h datasets are not plotted for clarity.

Grahic Jump Location
Fig. 6

Microspreading resistance of thick TXV substrates. Each point is the intercept of the linear asymptote for datasets of the type in Fig. 5 (there were three not included for clarity). The curve is the correlation given by Eq. (10).

Grahic Jump Location
Fig. 7

Unit cell for investigating the effect of material contact. Lateral dimensions, via, and substrate material are held constant. Film conductivity and substrate thickness are varied. After demonstrating the limiting case of thick films, film thickness and the varying upper boundary are held constant.

Grahic Jump Location
Fig. 8

Evolution of keff,z of a TXV array as an adhered film increases in thickness. Film conductivity is 40 W/m K, and substrate thickness is 200 μm.

Grahic Jump Location
Fig. 9

keff,z versus contacting material thermal conductivity for different substrate/cell thicknesses

Grahic Jump Location
Fig. 10

Microspreading resistance versus contacting material conductivity. Each point is obtained from FEM data in Fig. 9. The curve is the correlation given by Eq. (11).

Grahic Jump Location
Fig. 11

Maximum cell spreading resistance as a function of nondimensional via diameter and conductivity

Grahic Jump Location
Fig. 12

Value of the discount factor, f, for all 1200 axisymmetric cells. The points that fall farthest from the curve are those cells with the smallest via diameters. Circles correspond to the convection boundary condition, while diamonds correspond to film contact.

Grahic Jump Location
Fig. 13

Detail view of data in Fig. 12, with ± 15% bounds on ζ plotted. Cells with (d/P*)< 0.18 are excluded.

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In