In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.