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Research Papers

Impact Isolation Through the Use of Compliant Interconnects for Microelectronic Packages

[+] Author and Article Information
Wei Chen, Anirudh Bhat

Computer-Aided Simulation of Packaging
Reliability (CASPaR) Laboratory,
The George W. Woodruff School of
Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332-0405

Suresh K. Sitaraman

Computer-Aided Simulation of Packaging
Reliability (CASPaR) Laboratory,
The George W. Woodruff School of
Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332-0405
e-mail: suresh.sitaraman@me.gatech.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received June 30, 2014; final manuscript received September 16, 2015; published online October 12, 2015. Assoc. Editor: Susan Lu.

J. Electron. Packag 137(4), 041005 (Oct 12, 2015) (8 pages) Paper No: EP-14-1064; doi: 10.1115/1.4031680 History: Received June 30, 2014; Revised September 16, 2015

First-level and second-level compliant interconnect structures are being pursued in universities and industries to accommodate the differential displacement induced by the coefficient of thermal expansion mismatch between the die and the substrate or between the substrate and the board. The compliant interconnects mechanically decouple the die from the substrate or the substrate from the board, and thus reduce the thermally induced stresses in the assembly. This paper presents drop-test experimental and simulation data for scaled-up prototype of compliant interconnects. The simulations were based on Input-G method and performed using ANSYS® finite element software for varying drop heights. In parallel to the simulations, scaled-up compliant polymer interconnects sandwiched between a polymer die and a polymer substrate were fabricated using three-dimensional (3D) printing, and this fabrication provides a quick low-cost alternative to cleanroom fabrication. The prototype of the assembly was subjected to drop tests from varying drop heights. The response of the assembly during drop testing was captured using strain gauges and an accelerometer mounted on the prototype. The data from the experiments were compared with the predictions from the simulations. Based on such simulations, significant insight into the behavior of compliant interconnects under impact loading was obtained, which could be used for reliable design of compliant interconnect under impact loading. Both the experimental and simulation data reveal that the compliant interconnects are able to reduce the strains that transfer from substrate to die by one-order.

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References

JEDEC Standard JESD22-B111, 2013, “ Board Level Drop Test Method of Components for Handheld Electronic Products,” JEDEC Solid State Technology Association, Arlington, VA, Report No. JESD22-B111.
Luan, J.-e. , and Tee, T. Y. , 2004, “ Novel Board Level Drop Test Simulation Using Implicit Transient Analysis With Input-G Method,” 6th Electronics Packaging Technology Conference (EPTC 2004), Singapore, Dec. 8-10, pp. 671–677.
Tee, T. Y. , Luan, J.-e. , Pek, E. , Lim, C. T. , and Zhong, Z. , 2004, “ Novel Numerical and Experimental Analysis of Dynamic Responses Under Board Level Drop Test,” 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2004), Brussels, Belgium, May 10-12, pp. 133–140.
Luan, J.-e. , and Tee, T. Y. , 2005, “ Effect of Impact Pulse Parameters on Consistency of Board Level Drop Test and Dynamic Responses,” 55th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 31–June 3, pp. 665–673.
Pan, K. , Zhou, B. , and Yan, Y. , 2006, “ Simulating Analysis of Dynamic Responses for CSP Under Board Level Drop Test,” 7th International Conference on Electronic Packaging Technology (ICEPT’06), Shanghai, China, Aug. 26–29.
Chen, Z. , Wang, X. , Liu, Y. , and Liu, S. , 2010, “ Drop Test Simulation of 3D Stacked-Die Packaging With Input-G Finite Element Method,” 11th International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), Xi’an, China, Aug. 16-19, pp. 742–746.
Wong, E. , Lim, K. , Lee, N. , Seah, S. , Hoe, C. , and Wang, J. , 2002, “ Drop Impact Test—Mechanics & Physics of Failure,” 4th Electronics Packaging Technology Conference (EPTC), Singapore, Dec. 10-12, pp. 327–333.
Irving, S. , and Liu, Y. , 2004, “ Free Drop Test Simulation for Portable IC Package by Implicit Transient Dynamics FEM,” 54th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 1-4, pp. 1062–1066.
Lall, P. , Shantaram, S. , Angral, A. , and Kulkarni, M. , 2009, “ Explicit Submodeling and Digital Image Correlation Based Life-Prediction of Leadfree Electronics Under Shock-Impact,” 59th Electronic Components and Technology Conference (ECTC 2009), San Diego, CA, May 26–29, pp. 542–555.
Sun, Y. , and Pang, J. H. , 2008, “ Digital Image Correlation for Solder Joint Fatigue Reliability in Microelectronics Packages,” Microelectron. Reliab., 48(2), pp. 310–318. [CrossRef]
Chen, W. , Bhat, A. , and Sitaraman, S. K. , 2013, “ Use of Compliant Interconnects for Drop Impact Isolation,” 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC), Las Vega, NV, May 28–31, pp. 835–839.
Tribe, A. , Garraway, K. , Daborn, P. M. , and Miles, K. , 2007, “ The Use of Rapid Prototypes for Model Validation,” IMAC XXV, Orlando, FL, Feb. 19-22.
Mahn, J. , and Bayly, P. , 1999, “ Impact Testing of Stereolithographic Models to Predict Natural Frequencies,” J. Sound Vib., 224(3), pp. 411–430. [CrossRef]
Lee, R. E. , Okereke, R. , and Sitaraman, S. K. , 2011, “ Multi-Path Fan-Shaped Compliant Off-Chip Interconnects,” 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 31–June 3, pp. 2141–2145.
Seah, S. , Lim, C. , Wong, E. , Tan, V. , and Shim, V. , 2002, “ Mechanical Response of PCBs in Portable Electronic Products During Drop Impact,” 4th Electronics Packaging Technology Conference (EPTC), Singapore, Dec. 10-12, pp. 120–125.
Gibson, I. , Goenka, G. , Narasimhan, R. , and Bhat, N. , 2010, “ Design Rules for Additive Manufacture,” International Solid Freeform Fabrication Symposium (SFF), Austin, TX, Aug. 9-11, pp. 705–716.
Chen, W. , Okereke, R. , and Sitaraman, S. K. , 2013, “ Compliance Analysis of Multi-Path Fan-Shaped Interconnects,” Microelectron. Reliab., 53(7), pp. 964–974. [CrossRef]

Figures

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Fig. 1

Image on the left shows 3D model of three-arc compliant interconnect; image on the right shows the compliant interconnect printed by Objet Eden 250 system

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Fig. 2

Three-arc compliant interconnect drop-test sample shows a 3 × 3 area-array of three-arc compliant interconnects between a polymer die and a polymer substrate with four corner holes for drop-test mounting

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Fig. 3

Custom drop-test fixture bolted to crosshead of Instron Dynatup® 8250 drop weight impact tester

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Fig. 4

Accelerometer and strain gauge positions and orientations: (a) accelerometer and linear 1-axis strain gauge mounted on substrate (top view), (b) side view of mounted accelerometer and strain gauges, and (c) bi-axial tee-rosette strain gauge mounted on die (bottom view)

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Fig. 5

Measured acceleration for three-arc compliant interconnect assembly for drop heights equal to 50 mm and 150 mm: (a) 50 mm drop height acceleration data and (b) 150 mm drop height acceleration data

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Fig. 6

Experimental strain data for three-arc compliant interconnect drop tests with a drop height equal to 50 mm: (a) ε1, (b) ε2, and (c) ε3

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Fig. 7

Experimental strain data for three-arc compliant interconnect drop tests with a drop height equal to 150 mm: (a) ε1, (b) ε2, and (c) ε3

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Fig. 8

Close-up mesh of three-arc compliant interconnect array model used in the drop-test simulation

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Fig. 9

Flowchart describing the Input-G method and locations where the prescribed displacement boundary conditions are applied

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Fig. 10

Contour plot of the nodal von Mises stress (Pa) in the interconnects for a drop height of 200 mm during maximum deformation

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Fig. 11

Measured acceleration curve and two half-sine acceleration pulse curves with different impact times for one of the 50 mm drop events

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Fig. 12

Velocity and displacement curves obtained from the measured acceleration pulse and two half-sine acceleration pulse approximations with different impact times for one of the 50 mm drop events. (a) Velocity curves and (b) displacement curves.

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Fig. 13

Velocity and displacement curves by integrating measured acceleration curves for three 50 mm drop-test events: (a) velocity curves for 50 mm height drop-test and (b) displacement curves for 50 mm height drop-test

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Fig. 14

Mesh size control for the one-quarter of the actual flip-chip package system (a) side view of the finite element mesh; (b) top view of the finite element mesh; (c) zoomed-in view of the finite element mesh (from top to bottom: silicon die, compliant interconnects, and FR-4 substrate); and (d) isometric view of the finite element mesh

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