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Review Article

A Review of Two-Phase Forced Cooling in Three-Dimensional Stacked Electronics: Technology Integration

[+] Author and Article Information
Craig Green, Peter Kottke, Xuefei Han, Casey Woodrum, Pouya Asrar, Yogendra Joshi, Andrei Fedorov, Suresh Sitaraman

G. W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
771 Ferst Drive,
Atlanta, GA 30332

Thomas Sarvey, Xuchen Zhang, Muhannad Bakir

School of Electrical and Computer Engineering,
Georgia Institute of Technology,
777 Atlantic Drive NW,
Atlanta, GA 30332

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 22, 2015; final manuscript received August 30, 2015; published online September 25, 2015. Assoc. Editor: Mehdi Asheghi.

J. Electron. Packag 137(4), 040802 (Sep 25, 2015) (9 pages) Paper No: EP-15-1068; doi: 10.1115/1.4031481 History: Received July 22, 2015; Revised August 30, 2015

Three-dimensional (3D) stacked electronics present significant advantages from an electrical design perspective, ranging from shorter interconnect lengths to enabling heterogeneous integration. However, multitier stacking exacerbates an already difficult thermal problem. Localized hotspots within individual tiers can provide an additional challenge when the high heat flux region is buried within the stack. Numerous investigations have been launched in the previous decade seeking to develop cooling solutions that can be integrated within the 3D stack, allowing the cooling to scale with the number of tiers in the system. Two-phase cooling is of particular interest, because the associated reduced flow rates may allow reduction in pumping power, and the saturated temperature condition of the coolant may offer enhanced device temperature uniformity. This paper presents a review of the advances in two-phase forced cooling in the past decade, with a focus on the challenges of integrating the technology in high heat flux 3D systems. A holistic approach is applied, considering not only the thermal performance of standalone cooling strategies but also coolant selection, fluidic routing, packaging, and system reliability. Finally, a cohesive approach to thermal design of an evaporative cooling based heat sink developed by the authors is presented, taking into account all of the integration considerations discussed previously. The thermal design seeks to achieve the dissipation of very large (in excess of 500 W/cm2) background heat fluxes over a large 1 cm × 1 cm chip area, as well as extreme (in excess of 2 kW/cm2) hotspot heat fluxes over small 200 μm × 200 μm areas, employing a hybrid design strategy that combines a micropin–fin heat sink for background cooling as well as localized, ultrathin microgaps for hotspot cooling.

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Figures

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Fig. 1

Schematic of a typical two-phase forced flow heat sink embedded in 3D system

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Fig. 2

Schematic of the F2/S2 hybrid heat-sink concept

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Fig. 3

Ratio of thermal conductivity to microgap height (k/H), which serves as a proxy for heat transfer coefficient, as a function of outlet pressure for a variety of coolants [36]

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Fig. 4

Scanning electron microscopy images of the fabricated electrical microbumps (25 μm diameter), fluidic microbumps (210 μm OD), fluidic via (100 μm), and micropin–fins (150 μm) [61,62]

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Fig. 5

Schematic of the 3D STAECOOL design

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Fig. 6

Micropin–fin heat sink [34]

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Fig. 7

Micropin–fin sample fabrication process

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Fig. 8

Flow loop for characterizing micropin–fin heat sinks

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Fig. 9

Max wall temperature versus heat flux: 30 μm pin diameter, 60 μm pitch DI water at 1784 kg/m2 s [34]

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Fig. 10

Schematic of 5 μm × 200 μm × 300 μm microgap with aligned Pt heaters [63]

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Fig. 11

Temperature variation in the streamwise direction along the hotspot under varying thermal loads [63]

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Fig. 12

Schematic of computational domain modeled for mechanical stress analysis

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Fig. 13

Close-up view up computational domain for thermomechanical modeling showing TSVs, oxide layer, and Si pins

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Fig. 14

Shear stress near the top of TSVs showing concentration in oxide liner (stress in MPa)

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Fig. 15

Stress results (MPa) versus assumed copper stress-free temperature (°C)

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